WO1997011483A3 - Verfahren zum erzeugen sehr kleiner strukturweiten auf einem halbleitersubstrat - Google Patents

Verfahren zum erzeugen sehr kleiner strukturweiten auf einem halbleitersubstrat Download PDF

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Publication number
WO1997011483A3
WO1997011483A3 PCT/DE1996/001697 DE9601697W WO9711483A3 WO 1997011483 A3 WO1997011483 A3 WO 1997011483A3 DE 9601697 W DE9601697 W DE 9601697W WO 9711483 A3 WO9711483 A3 WO 9711483A3
Authority
WO
WIPO (PCT)
Prior art keywords
producing
small structural
semiconductor substrate
layer
structural widths
Prior art date
Application number
PCT/DE1996/001697
Other languages
English (en)
French (fr)
Other versions
WO1997011483A2 (de
Inventor
Martin Kerber
Original Assignee
Siemens Ag
Martin Kerber
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Martin Kerber filed Critical Siemens Ag
Priority to EP96938929A priority Critical patent/EP0852064A2/de
Priority to JP9512303A priority patent/JPH11512568A/ja
Publication of WO1997011483A2 publication Critical patent/WO1997011483A2/de
Publication of WO1997011483A3 publication Critical patent/WO1997011483A3/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

Verfahren zum Erzeugen einer sehr kleinen Strukturweite auf einem Halbleitersubstrat (1; 10) durch Erzeugen einer Mikrostruktur (8; 70) als Ergebnis einer isotropen Ätzung einer über eine Kante abgeschiedenen ersten Schicht (6) und Entfernen der die Kante bildenden Struktur (7; 60), wobei die Weite der Mikrostruktur (8; 70) etwa gleich der Dicke der abgeschiedenen ersten Schicht ist. Danach wird eine darunter liegende Polysiliziumschicht (5; 50) selektiv oxidiert. Die kleine Strukturweite kann der Querschnitt durch den Kanal einer Flash-Speicherzelle sein.
PCT/DE1996/001697 1995-09-19 1996-09-10 Verfahren zum erzeugen sehr kleiner strukturweiten auf einem halbleitersubstrat WO1997011483A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP96938929A EP0852064A2 (de) 1995-09-19 1996-09-10 Verfahren zum erzeugen sehr kleiner strukturweiten auf einem halbleitersubstrat
JP9512303A JPH11512568A (ja) 1995-09-19 1996-09-10 半導体基板上に極小パターン幅を形成するための方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19534780A DE19534780A1 (de) 1995-09-19 1995-09-19 Verfahren zum Erzeugen sehr kleiner Strukturweiten auf einem Halbleitersubstrat
DE19534780.3 1995-09-19

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/044,533 Continuation US6027972A (en) 1995-09-19 1998-03-19 Method for producing very small structural widths on a semiconductor substrate

Publications (2)

Publication Number Publication Date
WO1997011483A2 WO1997011483A2 (de) 1997-03-27
WO1997011483A3 true WO1997011483A3 (de) 1997-06-12

Family

ID=7772595

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1996/001697 WO1997011483A2 (de) 1995-09-19 1996-09-10 Verfahren zum erzeugen sehr kleiner strukturweiten auf einem halbleitersubstrat

Country Status (8)

Country Link
US (1) US6027972A (de)
EP (1) EP0852064A2 (de)
JP (1) JPH11512568A (de)
KR (1) KR19990044687A (de)
CN (1) CN1202981A (de)
DE (1) DE19534780A1 (de)
RU (1) RU2168797C2 (de)
WO (1) WO1997011483A2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19643185C2 (de) * 1996-10-18 1998-09-10 Siemens Ag Dual-Gate-Speicherzelle und Verfahren zur Herstellung einer nichtflüchtigen Speicherzelle
US6150245A (en) * 1997-02-27 2000-11-21 Nec Corporation Method of manufacturing a field effect transistor
JP4081854B2 (ja) * 1998-05-11 2008-04-30 沖電気工業株式会社 半導体装置の製造方法
JP2002100688A (ja) 2000-09-22 2002-04-05 Oki Electric Ind Co Ltd 不揮発性半導体メモリの製造方法
US6740557B1 (en) 2001-07-02 2004-05-25 Taiwan Semiconductor Manufacturing Company Spacer like floating gate formation
ITMI20022785A1 (it) * 2002-12-30 2004-06-30 St Microelectronics Srl Processo per la fabbricazione di celle di memoria
ITMI20022784A1 (it) * 2002-12-30 2004-06-30 St Microelectronics Srl Processo per la fabbricazione di celle di memoria
US20050239250A1 (en) * 2003-08-11 2005-10-27 Bohumil Lojek Ultra dense non-volatile memory array
JP2005183763A (ja) * 2003-12-22 2005-07-07 Toshiba Microelectronics Corp 不揮発性メモリを含む半導体装置の製造方法
DE102006037045B4 (de) * 2006-08-08 2011-05-05 Infineon Technologies Austria Ag Herstellungsverfahren zum Erzeugen einer Halbleitervorrichtung
CN107437548B (zh) * 2016-05-26 2020-03-10 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法、电子装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4513397A (en) * 1982-12-10 1985-04-23 Rca Corporation Electrically alterable, nonvolatile floating gate memory device
EP0197284A2 (de) * 1985-03-01 1986-10-15 Fujitsu Limited Verfahren zum Herstellen eines Halbleiter-Speicherbauelementes

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4558339A (en) * 1982-03-09 1985-12-10 Rca Corporation Electrically alterable, nonvolatile floating gate memory device
JP2547622B2 (ja) * 1988-08-26 1996-10-23 三菱電機株式会社 不揮発性半導体記憶装置
JPH05190809A (ja) * 1992-01-14 1993-07-30 Kawasaki Steel Corp 半導体装置の製造方法
US5236853A (en) * 1992-02-21 1993-08-17 United Microelectronics Corporation Self-aligned double density polysilicon lines for ROM and EPROM
US5225362A (en) * 1992-06-01 1993-07-06 National Semiconductor Corporation Method of manufacturing a full feature high density EEPROM cell with poly tunnel spacer
KR0150048B1 (ko) * 1994-12-23 1998-10-01 김주용 플래쉬 이이피롬 셀 및 그 제조방법
KR0166840B1 (ko) * 1995-05-12 1999-01-15 문정환 리세스 채널 구조를 갖는 반도체 소자 및 그의 제조방법
US5854501A (en) * 1995-11-20 1998-12-29 Micron Technology, Inc. Floating gate semiconductor device having a portion formed with a recess
DE69630864T2 (de) * 1996-01-31 2004-11-04 Sgs-Thomson Microelectronics S.R.L., Agrate Brianza Verfahren zur Herstellung nichtflüchtiger Speicheranordnungen mit Tunneloxid
US5750428A (en) * 1996-09-27 1998-05-12 United Microelectronics Corp. Self-aligned non-volatile process with differentially grown gate oxide thickness
US5786614A (en) * 1997-04-08 1998-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Separated floating gate for EEPROM application

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4513397A (en) * 1982-12-10 1985-04-23 Rca Corporation Electrically alterable, nonvolatile floating gate memory device
EP0197284A2 (de) * 1985-03-01 1986-10-15 Fujitsu Limited Verfahren zum Herstellen eines Halbleiter-Speicherbauelementes

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PARK T ET AL: "DOUBLE TRENCH ISOLATION (DTI): A NOVEL ISOLATION TECHNOLOGY FOR DEEP-SUBMICRON SILICON DEVICES", DIGEST OF TECHNICAL PAPERS OF THE SYMPOSIUM ON VLSI TECHNOLOGY, KYOTO, MAY 17 - 19, 1993, no. -, 17 May 1993 (1993-05-17), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 137/138, XP000462937 *

Also Published As

Publication number Publication date
KR19990044687A (ko) 1999-06-25
CN1202981A (zh) 1998-12-23
WO1997011483A2 (de) 1997-03-27
US6027972A (en) 2000-02-22
DE19534780A1 (de) 1997-03-20
JPH11512568A (ja) 1999-10-26
RU2168797C2 (ru) 2001-06-10
EP0852064A2 (de) 1998-07-08

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