EP0810651A2 - Procédé de fabrication d'une connexion entre les couches d'un câblage multicouche dans un dispositif semi-conducteur - Google Patents

Procédé de fabrication d'une connexion entre les couches d'un câblage multicouche dans un dispositif semi-conducteur Download PDF

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Publication number
EP0810651A2
EP0810651A2 EP97108640A EP97108640A EP0810651A2 EP 0810651 A2 EP0810651 A2 EP 0810651A2 EP 97108640 A EP97108640 A EP 97108640A EP 97108640 A EP97108640 A EP 97108640A EP 0810651 A2 EP0810651 A2 EP 0810651A2
Authority
EP
European Patent Office
Prior art keywords
wiring
conductor
layer
semiconductor device
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97108640A
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German (de)
English (en)
Other versions
EP0810651A3 (fr
Inventor
Shinya Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of EP0810651A2 publication Critical patent/EP0810651A2/fr
Publication of EP0810651A3 publication Critical patent/EP0810651A3/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Definitions

  • the present invention relates generally to a fabrication process of a semiconductor device. More specifically, the invention relates to a fabrication process of a semiconductor device which can stably form a connecting portion between multilayer wirings.
  • a connecting portion between multilayer wirings in a semiconductor device is generally formed in such a method that a lower wiring is patterned, an interlayer dielectric is formed on the wiring, a via hole is opened in the interlayer dielectric and metal is buried in the via hole. Associating with reduction of width of the wiring and diameter of the via hole, it is becoming difficult to establish alignment between the wiring and the via hole.
  • Fig. 1 is a section showing a conventional semiconductor device
  • Fig. 2 is a plan view showing a wiring of the conventional semiconductor device.
  • an interlayer insulation layer 2 is formed on a silicon substrate 1.
  • a first wiring 3 is formed by patterning.
  • a silicon oxide layer 4 is formed covering the first wiring 3.
  • a resist 5 is formed on the silicon oxide layer 4 by patterning.
  • a via hole 6 reaching the first wiring 3 is opened.
  • the via hole 6 can be out of alignment with the first wiring 3. Then, when the via hole 6 is etched, a reaction product is deposited to interfere conduction. Also, upon subsequently burying a conductor, if tungsten (W) is grown by CVD (Chemical Vapor Deposition), for example, a side wall of the first wiring 3 can be corroded by the reaction gas. Furthermore, due to the alignment error between the via hole 6 and the first wiring 3, a contact area of the via hole 6 and the first wiring 3 is reduced to increase resistance at the via hole.
  • CVD Chemical Vapor Deposition
  • Figs. 3A to 3G are sections showing process steps in a conventional fabrication process of a semiconductor device in sequential order.
  • an interlayer insulation layer 2 is formed on a silicon substrate 1, in which not shown elements and contacts are formed.
  • a first aluminum layer 10 is deposited in a thickness of about 2 ⁇ m. It should be noted that when the semiconductor device becomes a product at the end, the aluminum layer 10 functions as a first wiring. However, the thickness to be deposited at this step should be thicker than that required as the first wiring. Then, a resist 11 of a predetermined shape is formed on the first aluminum layer 10.
  • a resist 12 is formed in a region connecting the first wiring and a second wiring to be formed afterward.
  • anisotropic etching is again performed for the first aluminum layer 10.
  • the thickness of the first aluminum layer 10 becomes about 1 ⁇ m
  • anisotropic etching is terminated.
  • the first wiring 13 is formed on the interlayer insulation layer 2.
  • a columnar projection 14 is formed as a connecting portion between the first wiring and the second wiring. Then, the resist 12 is removed.
  • a silicon oxide layer is deposited over the entire surface to form an interlayer insulation layer 15.
  • the interlayer insulation layer 15 is etched until the top end surface of the columnar projection 14 is exposed. It should be noted that, upon performing the etching, when the surface of the interlayer insulation layer 15 is substantially flat, etchback is performed for entire surface. On the other hand, when unevenness is formed on the surface, for example, a resist or so forth is applied to make the surface flat and subsequently etching back is performed.
  • a second aluminum layer 16 is deposited in a thickness of about 1 ⁇ m over the entire surface.
  • anisotropic etching is performed to the second wiring 17.
  • the first wiring 13 and the second wiring 17 are electrically connected through the columnar projection 14.
  • a fabrication process of a semiconductor device comprises the steps of forming an interlayer insulation layer on a semiconductor substrate, forming a groove of a wiring shape in the interlayer insulation layer, burying a conductor in the groove, covering a part of the conductor with a masking material, removing a part of the conductor to form a recess with taking the masking material as a mask, thereby defining a first wiring at a lower part of the conductor under the recess and a columnar projection at a side of the recess on the first wiring, burying an insulation layer in the recess except for the upper surface of the columnar projection and forming a second wiring covering at least a part of the exposed upper surface of the columnar projection.
  • the masking material may have a shape provided a greater width than the width of the first wiring at the portion where the columnar projection is formed.
  • the step of burying the conductor in the groove may comprise the steps of burying a first conductor layer in the groove and burying a second conductor layer having greater etching speed than the first conductor layer on the first conductor layer in the groove, and the step of removing a part of the conductor may comprise a step of removing only the second conductor layer by way of selective etching.
  • the conductor may be one kind of metal selected from a group consisted of aluminum, copper, tungsten and polycrystalline silicon.
  • the first conductor may be one kind of metal selected from a group consisted of copper formed by electroless plating, copper formed by selective CVD, tungsten and polycrystalline silicon.
  • the second conductor layer may be one kind of metal selected from a group consisted of aluminum, copper, tungsten and polycrystalline silicon.
  • the step of forming the interlayer insulation layer may comprise a step of forming a interlayer insulation layer on the semiconductor substrate, and the step of forming the groove may comprise the steps of forming a resist on the interlayer insulation layer and performing anisotropic etching of the interlayer insulation layer with taking the resist as a mask.
  • the step of burying the conductor in the groove may comprise the steps of burying a conductor layer in the groove by CVD and flattening the surface of the conductor layer at the same height as that of the interlayer insulation layer by CMP.
  • the step of burying the insulation layer in the recess may comprise the steps of forming a interlayer insulation layer over the entire surface and flattening the surface of the interlayer insulation layer at the same height as that of the interlayer insulation layer by CMP.
  • the step of forming the second wiring may comprise the steps of forming a conductor layer over the entire surface, forming a resist on the conductor layer and forming a second wiring by etching of the conductor layer with taking the resist as a mask.
  • the connecting portion can be formed stably irrespective of the layout pattern of the first wiring.
  • the connecting portion having the same width as that of the first wiring can be formed in self-align manner. Therefore, no alignment error may be caused between the first wiring and the connecting portion. Thus, the highly reliable connecting portion with low resistance can be formed.
  • the connecting portion having a predetermined height can be formed with high accuracy.
  • the first embodiment of a fabrication process of a semiconductor device according to the present invention is constructed with a wiring groove forming step, a groove burying step, an insulation layer burying step and a second wiring forming step.
  • Figs. 4A to 4F are sections showing the process steps in the first embodiment of a fabrication process of a semiconductor device according to the present invention, illustrated in sequential order.
  • an interlayer insulation layer 2 is formed on a silicon substrate 1.
  • a silicon oxide layer 20 is formed on the interlayer insulation layer 2 in a thickness of 2 ⁇ m, for example.
  • a resist is applied on the silicon oxide layer 20.
  • a resist 21 is formed in a region which is not a region where the first wiring is to be formed.
  • anisotropic etching is performed to form a groove of the same shape as that of the first wiring, namely a wiring groove 22 in the silicon oxide layer 20.
  • the resist 21 is removed.
  • an aluminum layer is formed within the wiring groove 22.
  • the surface of the aluminum layer is flattened to the same height as that of the silicon oxide layer 20 by CMP (Chemical Mechanical Polishing).
  • CMP Chemical Mechanical Polishing
  • Fig. 5 is a plan view showing a resist for forming a columnar projection of the first embodiment of the semiconductor device according to the present invention.
  • a resist is applied on the first aluminum layer 23, and a resist 24 having greater width than that of a first wiring 25 to be formed afterward is formed in a region where a connecting portion between the first wiring and a second wiring 30 to be formed afterward by way of lithography.
  • a part of the aluminum layer 23 not covered by the resist 24 is etched up to about 1 ⁇ m by way of anisotropic etching.
  • the first wiring 25 is formed within the wiring groove 22.
  • a columnar projection 26 having the same width as the first wiring 25 as the connecting portion between the first wiring 25 and the second wiring 30 is formed in self-align manner.
  • the resist 24 is removed.
  • a silicon oxide is deposited.
  • the silicon oxide layer 28 having a flat surface is buried within the groove 27 on the first wiring 25 by polishing the silicon oxide until the upper surface of the columnar projection 26 is exposed by CMP and so forth.
  • Fig. 4F shows a plan view showing the wiring of the first embodiment of the semiconductor device according to the present invention, in which a section along line B-B corresponds to Fig. 4F.
  • the first wiring 25 and the second wiring 30 are electrically connected via the columnar projection 26 which has the same width as that of the first wiring 25.
  • the silicon oxide layer 20 having the same height as that of the first aluminum layer 23 has been formed around the first aluminum layer 23 to be the first wiring 25 later. Therefore, the resist layer can be formed uniformly so that the columnar projection 26 may be formed stably irrespective of the wiring pattern of the first wiring 25. Furthermore, since the wiring and the connecting portion are formed with one kind of conductor, number of the process steps can be reduced and fabrication period can be shortened.
  • the conductor to be used in the wiring or so forth should not be limited to aluminum, and copper, tungsten, polycrystalline silicon and the like can be used.
  • the second embodiment of a fabrication process of the present invention also consists of a wiring groove forming step, a groove burying step, an insulation layer burying step and a second wiring forming step, similarly to the first embodiment.
  • Figs. 7A to 7F are sections showing process steps in the second embodiment of a fabrication process of a semiconductor device according to the present invention, illustrated in sequential order.
  • an interlayer insulation layer 2 is formed on a silicon substrate 1.
  • the silicon oxide layer 20 is formed in a thickness of about 2 ⁇ m.
  • a resist is applied over the silicon oxide layer 20.
  • a resist 21 is formed in a region which is not a region where a first wiring is to be formed.
  • anisotropic etching is performed for the silicon oxide layer 20 to form a groove having the shape corresponding to the first wiring, namely a wiring groove 22.
  • a copper layer 31 in a thickness of 1 ⁇ m is formed within the wiring groove 22 by way of electroless plating, for example.
  • an aluminum layer is formed in a thickness of about 1 ⁇ m by way of CVD method, for example.
  • CMP is performed to polish the surface of the aluminum layer to be equal height to the silicon oxide 20 and to make the surface flat.
  • a resist is applied over the first aluminum layer 32.
  • a resist 33 is formed in a region where a connecting portion between a first wiring 34 and a second wiring 37 which are to be formed afterward by way of lithographic method.
  • anisotropic etching is performed for a part of the first aluminum layer 32 not covered with the resist 33.
  • etching is performed under the condition to have large ratio of the etching rate between the first aluminum layer 32 and the copper layer 31.
  • the etching speed becomes lowered significantly.
  • the first aluminum layer 32 can be selectively etched easily.
  • the first wiring 34 of copper is formed within the wiring groove 22.
  • a columnar projection 35 of aluminum serving as the connecting portion between the first wiring 31 and the second wiring 37 is formed.
  • a groove is formed between the columnar projection 35 on the first wiring 34 and the silicon oxide layer 20.
  • the resist 33 is removed.
  • a silicon oxide is deposited and subsequently the silicon oxide layer 36 with flat surface is buried within the groove on the first wiring 34 by polishing the silicon oxide layer until the top end surface of the columnar projection 35 is exposed by CMP and so forth.
  • a second aluminum layer is deposited in a thickness of about 1 ⁇ m.
  • the second wiring 37 is formed by performing anisotropic etching with taking a not shown resist of a predetermined shape.
  • the first wiring 34 and the second wiring 37 are electrically connected via the columnar projection 35.
  • the columnar projection 35 and the first wiring 34 by employing the different conductors in the columnar projection 35 and the first wiring 34, and anisotropic etching is performed under the condition where the etching speed of the conductor forming the columnar projection 35 is much higher than that of the first wiring 34. Therefore, end point of etching can be easily detected. Thus, the columnar projection of the desired height and the first wiring can be formed with high accuracy.
  • the conductor to be used in the first wiring is not limited to copper formed by electroless plating method, and copper formed by selective CVD, tungsten, polycrystalline silicon and so forth may be used. Also, the conductor to be used in the columnar projection is not limited to aluminum, and copper, tungsten, polycrystalline silicon and so forth can be used.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
EP97108640A 1996-05-29 1997-05-28 Procédé de fabrication d'une connexion entre les couches d'un câblage multicouche dans un dispositif semi-conducteur Withdrawn EP0810651A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP135530/96 1996-05-29
JP8135530A JP3068462B2 (ja) 1996-05-29 1996-05-29 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
EP0810651A2 true EP0810651A2 (fr) 1997-12-03
EP0810651A3 EP0810651A3 (fr) 1998-09-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP97108640A Withdrawn EP0810651A3 (fr) 1996-05-29 1997-05-28 Procédé de fabrication d'une connexion entre les couches d'un câblage multicouche dans un dispositif semi-conducteur

Country Status (4)

Country Link
US (1) US5773365A (fr)
EP (1) EP0810651A3 (fr)
JP (1) JP3068462B2 (fr)
KR (1) KR100244783B1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6943365B2 (en) * 1999-03-25 2005-09-13 Ovonyx, Inc. Electrically programmable memory element with reduced area of contact and method for making same
JP3920590B2 (ja) * 2000-06-19 2007-05-30 株式会社東芝 半導体装置の製造方法
US6352917B1 (en) * 2000-06-21 2002-03-05 Chartered Semiconductor Manufacturing Ltd. Reversed damascene process for multiple level metal interconnects
KR20020086098A (ko) * 2001-05-11 2002-11-18 아남반도체 주식회사 다층 배선의 콘택 구조 및 그 형성 방법
US7659192B2 (en) * 2006-12-29 2010-02-09 Intel Corporation Methods of forming stepped bumps and structures formed thereby
JP5931428B2 (ja) * 2011-12-15 2016-06-08 株式会社東芝 配線パターンの形成方法及び半導体装置
US11101175B2 (en) 2018-11-21 2021-08-24 International Business Machines Corporation Tall trenches for via chamferless and self forming barrier
US11139201B2 (en) 2019-11-04 2021-10-05 International Business Machines Corporation Top via with hybrid metallization
US11205591B2 (en) 2020-01-09 2021-12-21 International Business Machines Corporation Top via interconnect with self-aligned barrier layer
US11244897B2 (en) 2020-04-06 2022-02-08 International Business Machines Corporation Back end of line metallization
US11189528B2 (en) 2020-04-22 2021-11-30 International Business Machines Corporation Subtractive RIE interconnect
US11361987B2 (en) 2020-05-14 2022-06-14 International Business Machines Corporation Forming decoupled interconnects
US11942424B2 (en) 2021-12-01 2024-03-26 International Business Machines Corporation Via patterning for integrated circuits

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5055426A (en) * 1990-09-10 1991-10-08 Micron Technology, Inc. Method for forming a multilevel interconnect structure on a semiconductor wafer
JPH0758204A (ja) * 1993-08-17 1995-03-03 Nippon Steel Corp 半導体装置の製造方法
WO1997022144A1 (fr) * 1995-12-14 1997-06-19 Advanced Micro Devices, Inc. Structures vias a damasquinage inverse

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JPS5656654A (en) * 1979-10-15 1981-05-18 Fujitsu Ltd Manufacture of semiconductor device
JPS59125640A (ja) * 1982-12-28 1984-07-20 Fujitsu Ltd 半導体装置の製造方法
JPH04226054A (ja) * 1990-03-02 1992-08-14 Toshiba Corp 多層配線構造を有する半導体装置及びその製造方法
JPH04186627A (ja) * 1990-11-16 1992-07-03 Mitsubishi Electric Corp 半導体装置
JP3123092B2 (ja) * 1991-03-06 2001-01-09 日本電気株式会社 半導体装置の製造方法
JPH05102314A (ja) * 1991-03-20 1993-04-23 Oki Electric Ind Co Ltd 半導体装置の多層配線形成方法
JPH04303943A (ja) * 1991-03-30 1992-10-27 Nec Corp 半導体装置の製造方法
US5453154A (en) * 1991-10-21 1995-09-26 National Semiconductor Corporation Method of making an integrated circuit microwave interconnect and components
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JPH0637190A (ja) * 1992-07-14 1994-02-10 Mitsubishi Electric Corp 半導体装置およびその製造方法
EP0608628A3 (fr) * 1992-12-25 1995-01-18 Kawasaki Steel Co Procédé pour fabriquer un dispositif semi-conducteur ayant une structure d'interconnexion multi-couches.
US5602053A (en) * 1996-04-08 1997-02-11 Chartered Semidconductor Manufacturing Pte, Ltd. Method of making a dual damascene antifuse structure

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
US5055426A (en) * 1990-09-10 1991-10-08 Micron Technology, Inc. Method for forming a multilevel interconnect structure on a semiconductor wafer
JPH0758204A (ja) * 1993-08-17 1995-03-03 Nippon Steel Corp 半導体装置の製造方法
WO1997022144A1 (fr) * 1995-12-14 1997-06-19 Advanced Micro Devices, Inc. Structures vias a damasquinage inverse

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Also Published As

Publication number Publication date
KR100244783B1 (ko) 2000-03-02
EP0810651A3 (fr) 1998-09-30
KR970075681A (ko) 1997-12-10
JP3068462B2 (ja) 2000-07-24
JPH09321138A (ja) 1997-12-12
US5773365A (en) 1998-06-30

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