EP0528290B1 - Halbleiteranordnung und Verfahren zu ihrer Herstellung - Google Patents

Halbleiteranordnung und Verfahren zu ihrer Herstellung Download PDF

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Publication number
EP0528290B1
EP0528290B1 EP92113472A EP92113472A EP0528290B1 EP 0528290 B1 EP0528290 B1 EP 0528290B1 EP 92113472 A EP92113472 A EP 92113472A EP 92113472 A EP92113472 A EP 92113472A EP 0528290 B1 EP0528290 B1 EP 0528290B1
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Prior art keywords
gate electrode
layer
semiconductor
insulating layer
forming
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French (fr)
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EP0528290A1 (de
Inventor
Teruhiko Okada
Hirotada c/o Mitsubishi Denki K.K. LSI Kuriyama
Yoshio c/o Mitsubishi Denki K.K. LSI Kohno
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

Definitions

  • the present invention relates generally to semiconductor devices and manufacturing methods thereof, and more specifically, to a structure of a thin film transistor and a manufacturing method thereof. Description of the Background Art
  • TFT thin film transistor
  • a gate electrode 2 of polysilicon is formed on an interlayer insulating film 1 formed on a bulk transistor (not shown).
  • a gate oxide film 6 is formed along the top flat portion and sidewalls of the gate electrode 2.
  • a semiconductor layer 7 is formed along the gate oxide film 6. Formed at a position of the semiconductor layer 7 opposite to the gate electrode 2 is a channel region 7a. Source/drain regions 7b, 7c are formed at positions having the channel region 7a therebetween.
  • an interlayer insulating film 1 is formed as thick as 1500nm on a bulk transistor (not shown) by thermal chemical vapor deposition.
  • a polysilicon layer 2 to be the gate electrode 2 of the TFT is deposited as thick as 200nm on the interlayer insulating film 1 by means of thermal chemical vapor deposition.
  • a resist film 4 having a prescribed form is formed on the surface of the polysilicon layer 2 by a photolithography technique.
  • a resist film 4 is subjected to anisotropic reactive ion etching to form the gate electrode 2.
  • the resist film 4 is etched away.
  • an oxide film 6 for forming a gate oxide film having a thickness of 50nm is formed on the surfaces of the gate electrode 2 and the interlayer insulating film 1 by thermal CVD.
  • a polysilicon layer 7 to form the semiconductor layer of the TFT is deposited as thick as 50nm on the oxide film 6 by thermal chemical vapor deposition.
  • a resist film 8 is formed on the surface of the polysilicon layer 7.
  • the resist film 8 is patterned into a prescribed form by means of a photolithography technique or the like.
  • an impurity for example, 1 x 10 15 (cm -2 ) of boron for forming source/drain regions is implanted into the polysilicon layer 7.
  • the resist film 8 is etched away.
  • the TFT having a channel region 7a in the region of the polysilicon layer 7 opposite to the gate electrode 2 and the source/drain regions 7b, 7c at the positions having the channel region 7a therebetween.
  • the gate electrode 2 is formed by subjecting the polysilicon layer 7 to anisotropic reactive ion etching.
  • the gate electrode 2 therefore takes a substantially rectangular form.
  • substantially orthogonal edges 9, 9 are produced in the oxide film 6 the and polysilicon layer 7 formed along the gate electrode 2. Electric fields are likely to concentrate on these edges 9, 9, resulting in hot carriers or the like. The hot carriers enter into the gate oxide film 6, thus deteriorating the insulation of the gate oxide film 6.
  • CMOS EPROM HN27C256 discloses a 256 kbit CMOS EPROM adopting the poly-Si-PMOS technology in order to prevent latch-up.
  • An undoped region between the source and drain regions is used as a channel of the transistor.
  • the channel conductivity is controlled by a voltage applied to a well which is positioned underneath the poly-silicon channel and isolated therefrom through a thin SiO 2 layer.
  • the thickness of the SiO 2 layer is lower at the position under the gate electrode so that the transistor structure comprises a recess at the position of the channel region.
  • a semiconductor device comprising: a semiconductor substrate; semiconductor means provided at a prescribed distance apart from each other on said semiconductor substrate, said semiconductor means comprising gate electrodes formed on said semiconductor substrate; a further gate electrode formed between said gate electrodes of said semiconductor means with an insulating layer between said further gate electrode and each of said gate electrodes, respectively, said further gate electrode having a V-shape; a gate insulating layer on the upper surfaces of said further gate electrode and said insulating layer; and a semiconductor layer on said gate insulating layer, said semiconductor layer having a channel region of a first conductivity type opposing said further gate electrode and source/drain regions of a second conductivity type at the respective ends of said semiconductor layer; said channel region of said semiconductor layer essentially following said V-shape of said further gate electrode.
  • this object is also accomplished by a method of manufacturing a semiconductor device, comprising the steps of: forming gate electrodes on the surface of a semiconductor substrate; forming an insulating layer on the surface of said gate electrodes; forming a resist film at a prescribed position on the surface of said insulating layer and etching said insulating layer using said resist film as a mask; removing said resist film; forming a conductor layer on the surface of said insulating layer; forming a further resist film on the surface of said conductor layer; performing thermal oxidation using said further resist film as a mask and forming a further gate electrode having a V-shape; forming a gate insulating layer on the surfaces of said further gate electrode and said insulating layer; forming a semiconductor layer of a first conductivity type on the surface of said gate insulating layer; forming a mask on the surface of said semiconductor layer at a position opposing said further gate electrode, and forming a channel region of said first conductivity type at said position opposing said further
  • the present invention there is no channel layer of an orthogonal bent formed in the semiconductor layer formed on the gate electrodes with the gate insulating layer therebetween. This suppresses the concentration of electric fields as generated at the orthogonal bents of the conventional semiconductor device described with reference to Fig. 38. Furthermore, hot carriers can be prevented from being implanted into the gate insulating layer in the semiconductor device.
  • Fig. 1 is a cross sectional view showing a structure of a thin film transistor in accordance with a first embodiment of the present invention
  • TFT thin film transistor
  • the TFT according to the first embodiment has an interlayer insulating film 1 formed on a bulk transistor (not shown).
  • a gate electrode 2 having a central flat portion and inclined sidewalls descending rightward and leftward from the right and left ends of the central flat portion is formed on interlayer insulating film 1.
  • First insulating layers 5, 5 are formed in contact with and along the right and left ends of the central flat portion of the gate electrode and the inclined sidewalls.
  • a gate oxide film 6 which is a second insulating layer is formed on the surfaces of gate electrode 2 and first insulting layers 5, 5.
  • a semiconductor layer 7 of first type conductivity, for example, p type is formed on the surface of gate oxide film 6.
  • a P type channel region 7a is formed on the p type semiconductor layer at the position opposing the central flat portion.
  • Source/drain regions 7b, 7c of second type conductivity, for example, n type is formed at the positions of p type semiconductor layer 2 having channel region 7a therebetween.
  • interlayer insulating film 1 is formed on the bulk transistor (not shown).
  • a polysilicon layer 2 is deposited as thick as 200nm on interlayer insulating film 1 by means of thermal chemical vapor deposition.
  • a nitride film 3 having a thickness of 200nm is formed on polysilicon layer 2 by thermal CVD.
  • a resist film is applied onto nitride film 3. Thereafter, the resist film is patterned by a photolithography technique, to form a resist film 4 having a prescribed form.
  • nitride film 3 is subjected to anisotropic reactive etching to take a prescribed form.
  • first insulating layers 5, 5 are formed on the upper surface of polysilicon layer 2 by thermal oxidation in accordance with LOCOS process.
  • gate electrode 2 having the central flat portion and the inclined sidewalls descending rightward and leftward from the right and left ends of the central flat portion is thus formed.
  • a gate oxide film 6 having a thickness of 50nm is formed on the surfaces of gate electrode 2 and first insulating layers 5, 5 by means of thermal chemical vapor deposition.
  • a semiconductor layer, a polysilicon layer 7 is deposited as thick as 50nm on gate oxide film 6 by thermal CVD.
  • a resist film 4 having a prescribed form is formed on the surface of semiconductor layer 7 at the position opposite to the central flat portion of gate electrode 2. Using resist film 4 as mask, an impurity of second type conductivity, for example, n type is introduced at a prescribed position of semiconductor layer 7.
  • an impurity of second type conductivity for example, n type is introduced at a prescribed position of semiconductor layer 7.
  • channel region 7a of p type which is the first type conductivity is formed in semiconductor layer 7 at the position opposite to the central flat portion of gate electrode 2.
  • Source/drain regions 7b, 7c of n type which is the second type conductivity are formed at the positions having channel region 7a therebetween.
  • the bent angle is formed to be beyond 90° in the vicinities of the boundaries of channel region 7a and source/drain regions 7b, 7c.
  • Semiconductor layer 7 is therefore formed with no orthogonal bent produced. This allows the concentration of electric fields in channel region 7a to be suppressed.
  • the structure of the TFT in accordance with the second embodiment has a substantially identical structure to the TFT in the aforementioned first embodiment.
  • the gate electrode 2 of the TFT described above has a structure isolated from first insulating layers 5, 5.
  • the TFT in accordance with the second embodiment has polysilicon layer 2 for forming gate electrode 2 deposited thicker than usual.
  • gate electrode 2 exists on the entire surface of interlayer insulating film 1.
  • an interlayer insulating film 1 is formed on a bulk transistor (not shown).
  • a polysilicon layer 2 for forming a gate electrode is formed by thermal CVD on the interlayer insulating film as thick as 400nm which is thicker than the case of the first embodiment. Thereafter, going through the same manufacturing process as the TFT in accordance with the first embodiment, the TFT in accordance with the second embodiment is formed.
  • the bent angle is formed to be beyond 90° in the vicinities of the boundaries of channel region 7a and source/drain regions 7b, 7c, and, therefore, an orthogonal bent is not formed in semiconductor layer 7. This allows the concentration of electric fields to be suppressed in channel region 7a.
  • gate electrode 2 existing on the entire surface of interlayer insulating film 1, making a contact with gate electrode 2 is possible at an arbitrary position on the substrate.
  • a structure of a TFT in accordance with a third embodiment of the present invention follows.
  • the TFT in accordance with a third embodiment is formed between the gate electrode 10a and gate electrode 10b of the bulk transistor with sidewalls formed on a silicon substrate 20.
  • First insulating layers 11, 11 are formed on gate electrode 10a and gate electrode 10b.
  • the gate electrode 13 of the TFT having an approximately V shape is formed on first insulating layers 11, 11.
  • a gate oxide film 14 is formed on the surfaces of first insulating layers 11, 11 and gate electrode 13.
  • a channel layer 15 is formed on the upper surface of gate oxide film 14.
  • First insulating layer 11 is deposited as thick as 300nm on bulk transistors 10a and 10b by thermal chemical vapor deposition.
  • a resist film patterned into a prescribed form is formed on interlayer insulating film 11 by a photolithography technique.
  • first insulating layer 11 between bulk transistors 10a and 10b is removed away by anisotropic reactive ion etching, thereby forming an opening leading to semiconductor substrate 20.
  • resist film 12 is removed.
  • polysilicon layer 13 for gate electrode is deposited as thick as 300nm on interlayer insulating film 11 by thermal chemical vapor deposition. Thereafter, resist film 12 is applied onto polysilicon layer 13. Resist film 12 is then patterned into a prescribed form by a photolithography technique. Referring to Fig. 21, resist film 12 is removed. Thereafter, TFT gate electrode 13 is formed by anisotropic reactive ion etching.
  • gate oxide film 14 having a thickness of 50nm is formed on gate electrode 13 and first insulating layers 11, 11 by thermal CVD.
  • Polysilicon layer 15 for forming the TFT semiconductor layer is deposited as thick as 50nm on gate oxide film 14 by thermal CVD.
  • a resist film (not shown) is formed on the surface of polysilicon layer 15 opposite to gate electrode 13.
  • an impurity of the second type conductivity is introduced at a prescribed position of polysilicon layer 15.
  • polysilicon layer 15 is formed with no orthogonal bent formed.
  • Channel region 15a of first type conductivity, for example, p type is formed at the position opposite to gate oxide film 13.
  • Source/drain regions 15b, 15c of second type conductivity, for example, n type are formed at positions having channel region 15a therebetween.
  • the bent angle in the vicinities of the boundaries of channel region 15a and source/drain regions 15b, 15c is formed to be beyond 90°.
  • the concentration of electric fields can therefore be suppressed by the formation of the semiconductor layer with no orthogonal bent produced in the semiconductor layer.
  • the TFT in accordance with the fourth embodiment is formed immediately above the gate electrode 10 of bulk transistor.
  • a description of a manufacturing process of the TFT having this structure follows in conjunction with Figs. 24 to 29.
  • first insulating layer 11 is formed on the gate electrode 10 of the bulk transistor.
  • a semiconductor layer 15 formed of polysilicon is deposited on the surface of first insulating layer 11 by thermal CVD.
  • a gate oxide film 14 is formed on the semiconductor layer 15.
  • Gate electrode layer 13 is formed on gate oxide film 14.
  • a resist film 12 is applied onto gate electrode layer 13 and the structure is etched into a prescribed form by means of a photolithography technique.
  • gate electrode layer 13 and gate oxide film 14 are subjected to reactive anisotropic ion etching into prescribed forms.
  • resist film 12 is removed away.
  • an impurity of the second type conductivity is introduced into semiconductor layer 15.
  • a p type channel region 15a is formed in semiconductor layer 15 which is the lower portion of the gate electrode 13 of the TFT.
  • N source/drain regions 15b, 15c are formed in the right and left regions of semiconductor layer 15 having p channel region 15a therebetween.
  • the formation of the TFT immediately above bulk transistor 10 allows suppression of the concentration of electric fields at a bent, because the bent angle at each of the positions in the vicinities of the boundaries of channel region 15a and source/drain regions 15b, 15c is formed to be beyond 90° and an orthogonal bent is not formed in semiconductor layer 15.
  • a gate electrode 2 having a central flat portion and sidewalls formed broaden downwardly at a prescribed inclination with respect to both sides of the central flat portion is formed on an interlayer insulating film 1.
  • a gate oxide film 6 is formed along the central flat portion and sidewalls of gate electrode 2.
  • a semiconductor layer 7 is formed along the surface of gate oxide film 6.
  • a channel region 7a of first type conductivity, for example, p type is formed at the position opposite to the central flat portion of gate electrode 2.
  • Source/drain regions 7b, 7c of second type conductivity, for example, n type are formed at the positions having p type channel region 7a therebetween.
  • a polysilicon layer 2 to form a gate electrode is formed on interlayer insulating film 1.
  • resist film 4 is subjected to reactive anisotropic ion etching, thus, polysilicon layer 2 is formed to be gate electrode 2 corresponding to the form of resist film 4 and having a central flat portion and sidewalls formed broaden downwardly having a prescribed inclination with respect to both sides of the central flat portion.
  • resist film 4 is removed away.
  • a gate oxide film 6 is formed on gate electrode 2.
  • Semiconductor layer 7 is formed on gate oxide film 6.
  • resist film 4 having a prescribed form is formed in the area opposite to the surface of the semiconductor layer 7 of gate electrode 2.
  • an impurity of second type conductivity, for example, n type is introduced into semiconductor layer 7.
  • channel region 7a of the first type conductivity, for example, p type is formed in the region opposite to the gate electrode 2 of semiconductor layer 7.
  • Source/drain regions 7b, 7c of the second type conductivity, for example, n type are formed at the positions of semiconductor layer 7 having channel region 7a therebetween.
  • the bent angle in the vicinities of the boundaries of channel region 7a and source/drain regions 7b, 7c is formed to be beyond 90°, no orthogonal bent is formed in semiconductor layer 7, and, therefore, the concentration of electric fields in the orthogonal bent of the conventional semiconductor layer can be suppressed.
  • FIG. 37 a cross section of the TFT in accordance with the third embodiment used for an SRAM memory cell is shown.
  • the semiconductor layer formed in the thin film transistor is formed in such a manner that no orthogonal bent is produced.
  • the concentration of electric fields in the orthogonal bent of the semiconductor layer according to the conventional technique can be prevented.
  • hot carriers created by the concentration of electric fields can be suppressed from getting into the insulating film. Consequently, a stable operation of the semiconductor device is secured, and a highly reliable TFT can be provided.

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Claims (11)

  1. Halbleiteranordnung mit:
    einem Halbleitersubstrat (20),
    an einer festgelegten Entfernung voneinander auf dem Halbleitersubstrat (20) vorgesehenen Halbleitereinrichtungen, wobei die Halbleitereinrichtungen auf dem Halbleitersubstrat (20) ausgebildete Gate-Elektroden (10a, 10b) und eine zwischen den Gate-Elektroden (10a, 10b) der Halbleitereinrichtungen ausgebildete weitere Gate-Elektrode (13) jeweils mit einer Isolationsschicht (11) zwischen der weiteren Gate-Elektrode (13) und jeder der Gate-Elektroden (10a, 10b) aufweisen, wobei die weitere Gate-Elektrode (13) eine V-Form aufweist,
    einer Gate-Isolationsschicht (14) auf den oberen Oberflächen der weiteren Gate-Elektrode (13) und der Isolationsschicht (11) und
    einer Halbleiterschicht (15) auf der Gate-Isolationsschicht (14), wobei die Halbleiterschicht (15) einen der weiteren Gate-Elektrode (13) gegenüberliegenden Kanalbereich einer ersten Leitungsart (15a) und Source-/Drainbereiche (15b, 15c) einer zweiten Leitungsart an den jeweiligen Enden der Halbleiterschicht (15) aufweist, wobei der Kanalbereich der Halbleiterschicht (15) im wesentlichen die V-Form der weiteren Gate-Elektrode (13) nachfolgt.
  2. Halbleiteranordnung nach Anspruch 1, wobei die Gate-Isolationsschicht (14) die Oberfläche der Halbleiterschicht (15) an deren gesamten Bereich berührt und die weitere Gate-Elektrode (13) an zumindest dem Bereich der weiteren Gate-Elektrode (13) berührt, der dem Kanalbereich (15a) gegenüberliegt.
  3. Halbleiteranordnung nach Anspruch 1, wobei die weitere Gate-Elektrode (13), die Halbleiterschicht (15) und die Gate-Isolationsschicht (14) einen MOS-Feldeffekttransitor ausbilden.
  4. Halbleiteranordnung nach Anspruch 1, wobei die weitere Gate-Elektrode (13) eine mit Fremdatomen dotierte Polysiliziumschicht ist.
  5. Halbleiteranordnung nach Anspruch 1, wobei die Halbleiterschicht (15) eine mit Fremdatomen dotierte Polysiliziumschicht ist.
  6. Halbleiteranordnung nach Anspruch 1, wobei die Gate-Isolationsschicht (14) ein Siliziumoxidfilm ist.
  7. Verfahren zur Herstellung einer Halbleiteranordnung mit den Schritten:
    Ausbilden von Gate-Elektroden (10a, 10b) auf der Oberfläche eines Halbleitersubstrats (20),
    Ausbilden einer Isolationsschicht (11) auf der Oberfläche der Gate-Elektroden (10a, 10b),
    Ausbilden eines Resistfilms (12) an einer festgelegten Stelle auf der Oberfläche der Isolationsschicht (11) und Ätzen der Isolationsschicht (11) unter Verwendung des Resistfilms (12) als Maske,
    Entfernen des Resistfilms (12),
    Ausbilden einer Leitungsschicht (13) auf der Oberfläche der Isolationsschicht (11),
    Ausbilden eines weiteren Resistfilms (12) auf der Oberfläche der Leitungsschicht (13),
    Durchführen einer Wärmeoxidation unter Verwendung des weiteren Resistfilms (12) als Maske und Ausbilden einer weiteren Gate-Elektrode (13) mit einer V-Form,
    Ausbilden einer Gate-Isolationsschicht (14) auf den Oberflächen der weiteren Gate-Elektrode (13) und der Isolationsschicht (11),
    Ausbilden einer Halbleiterschicht (15) einer ersten Leitungsart auf der Oberfläche der Gate-Isolationsschicht (14),
    Ausbilden einer Maske auf der Oberfläche der Halbleiterschicht (15) an einer der weiteren Gate-Elektrode (13) gegenüberliegenden Stelle und Ausbilden eines Kanalbereichs (15a) der ersten Leitungsart durch Implantation von Fremdatomen einer zweiten Leitungsart an der der weiteren Gate-Elektrode (13) der Halbleiterschicht (15) der ersten Leitungsart gegenüberliegenden Stelle und von Source-/Drainbereichen (15b, 15c) der zweiten Leitungsart an Stellen mit dem dazwischenliegenden Kanalbereich (15a).
  8. Verfahren zur Herstellung einer Halbleiteranordnung nach Anspruch 7, wobei der Ausbildungsschritt der Leitungsschicht (13) durch Abscheiden von Polysilizium mittels dem thermischen CVD-Verfahren erfolgt.
  9. Verfahren zur Herstellung einer Halbleiteranordnung nach Anspruch 7, wobei der Ausbildungsschritt der Isolationsschicht (11) entsprechend einem LOCOS-Verfahren durch Wärmeoxidation einen Oxidfilm ausbildet.
  10. Verfahren zur Herstellung einer Halbleiteranordnung nach Anspruch 7, wobei der Ausbildungsschritt der Halbleiterschicht (15) durch Abscheiden von Polysilizium mittels dem thermischen CVD-Verfahren erfolgt.
  11. Verfahren zur Herstellung einer Halbleiteranordnung nach Anspruch 7, wobei der Ausbildungsschritt der Gate-Isolationsschicht (14) durch Wärmeoxidation einen Oxidfilm ausbildet.
EP92113472A 1991-08-08 1992-08-07 Halbleiteranordnung und Verfahren zu ihrer Herstellung Expired - Lifetime EP0528290B1 (de)

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EP96119724A EP0771035B1 (de) 1991-08-08 1992-08-07 Halbleiteranordnung und Verfahren zu ihrer Herstellung

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JP3199434A JP2901163B2 (ja) 1991-08-08 1991-08-08 半導体装置及びその製造方法
JP199434/91 1991-08-08

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EP0528290B1 true EP0528290B1 (de) 1997-06-18

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EP96119724A Expired - Lifetime EP0771035B1 (de) 1991-08-08 1992-08-07 Halbleiteranordnung und Verfahren zu ihrer Herstellung

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US (1) US5550390A (de)
EP (2) EP0528290B1 (de)
JP (1) JP2901163B2 (de)
KR (1) KR960012916B1 (de)
DE (2) DE69232381T2 (de)

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DE2503864C3 (de) * 1975-01-30 1981-09-24 Siemens AG, 1000 Berlin und 8000 München Halbleiterbauelement
JPS55132072A (en) * 1979-03-31 1980-10-14 Toshiba Corp Mos semiconductor device
JPS5688354A (en) * 1979-12-20 1981-07-17 Toshiba Corp Semiconductor integrated circuit device
JPS57132365A (en) * 1981-02-10 1982-08-16 Toshiba Corp Nonvolatile semiconductor memory storage
JPS58124261A (ja) * 1982-01-21 1983-07-23 Toshiba Corp 半導体装置
JPS58218169A (ja) * 1982-06-14 1983-12-19 Seiko Epson Corp 半導体集積回路装置
JPS59108360A (ja) * 1982-12-14 1984-06-22 Mitsubishi Electric Corp 半導体装置
JPH0616560B2 (ja) * 1982-12-17 1994-03-02 セイコー電子工業株式会社 薄膜トランジスタの製造方法
DE3533032A1 (de) * 1985-09-17 1987-03-19 Standard Elektrik Lorenz Ag Duennschicht-feldeffekt-transistor und ein verfahren zu seiner herstellung
JP2892683B2 (ja) * 1989-05-29 1999-05-17 株式会社日立製作所 半導体記憶装置およびその製造方法
JPS62190761A (ja) * 1986-02-18 1987-08-20 Nissan Motor Co Ltd 半導体装置
JPS63104373A (ja) * 1986-10-20 1988-05-09 Mitsubishi Electric Corp 半導体記憶装置
JPH01229229A (ja) * 1988-03-09 1989-09-12 Seikosha Co Ltd 非晶質シリコン薄膜トランジスタおよびその製造方法
JPH01268064A (ja) * 1988-04-20 1989-10-25 Hitachi Ltd 多結晶シリコン薄膜の形成方法
JPH01276672A (ja) * 1988-04-27 1989-11-07 Seikosha Co Ltd 逆スタガー型非晶質シリコン薄膜トランジスタ
JPH022175A (ja) * 1988-06-14 1990-01-08 Matsushita Electric Ind Co Ltd 薄膜トランジスタ及びその製造方法
JPH0348463A (ja) * 1989-03-01 1991-03-01 Mitsubishi Electric Corp 薄膜トランジスタ
JPH0341774A (ja) * 1989-07-10 1991-02-22 Sharp Corp 薄膜トランジスタ
JPH03293773A (ja) * 1990-04-12 1991-12-25 Casio Comput Co Ltd 薄膜トランジスタメモリ
JPH04505833A (ja) * 1990-10-05 1992-10-08 ゼネラル・エレクトリック・カンパニイ 基準構造の地形の伝搬地形による装置の自己アライメント
JPH04162668A (ja) * 1990-10-26 1992-06-08 Hitachi Ltd 半導体装置およびその製造方法

Also Published As

Publication number Publication date
EP0528290A1 (de) 1993-02-24
JP2901163B2 (ja) 1999-06-07
DE69220432T2 (de) 1998-01-22
KR960012916B1 (ko) 1996-09-25
EP0771035A1 (de) 1997-05-02
KR930005258A (ko) 1993-03-23
EP0771035B1 (de) 2002-01-23
JPH0547793A (ja) 1993-02-26
DE69232381D1 (de) 2002-03-14
DE69232381T2 (de) 2002-11-14
DE69220432D1 (de) 1997-07-24
US5550390A (en) 1996-08-27

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