DE69939518D1 - Sicherungs-Layout für ein verbessertes Verfahrensfenster zum Schmelzen der Sicherung - Google Patents

Sicherungs-Layout für ein verbessertes Verfahrensfenster zum Schmelzen der Sicherung

Info

Publication number
DE69939518D1
DE69939518D1 DE69939518T DE69939518T DE69939518D1 DE 69939518 D1 DE69939518 D1 DE 69939518D1 DE 69939518 T DE69939518 T DE 69939518T DE 69939518 T DE69939518 T DE 69939518T DE 69939518 D1 DE69939518 D1 DE 69939518D1
Authority
DE
Germany
Prior art keywords
fuse
melting
improved process
process window
backup
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69939518T
Other languages
English (en)
Inventor
Frank Prein
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE69939518D1 publication Critical patent/DE69939518D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
DE69939518T 1998-11-05 1999-09-24 Sicherungs-Layout für ein verbessertes Verfahrensfenster zum Schmelzen der Sicherung Expired - Fee Related DE69939518D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/186,515 US6121074A (en) 1998-11-05 1998-11-05 Fuse layout for improved fuse blow process window

Publications (1)

Publication Number Publication Date
DE69939518D1 true DE69939518D1 (de) 2008-10-23

Family

ID=22685256

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69939518T Expired - Fee Related DE69939518D1 (de) 1998-11-05 1999-09-24 Sicherungs-Layout für ein verbessertes Verfahrensfenster zum Schmelzen der Sicherung

Country Status (7)

Country Link
US (1) US6121074A (de)
EP (1) EP0999592B1 (de)
JP (1) JP4621319B2 (de)
KR (1) KR100695591B1 (de)
CN (1) CN1139123C (de)
DE (1) DE69939518D1 (de)
TW (1) TW424317B (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121074A (en) * 1998-11-05 2000-09-19 Siemens Aktiengesellschaft Fuse layout for improved fuse blow process window
DE19924153B4 (de) * 1999-05-26 2006-02-09 Infineon Technologies Ag Schaltungsanordnung zur Reparatur eines Halbleiterspeichers
US20030025177A1 (en) 2001-08-03 2003-02-06 Chandrasekharan Kothandaraman Optically and electrically programmable silicided polysilicon fuse device
US7375027B2 (en) 2004-10-12 2008-05-20 Promos Technologies Inc. Method of providing contact via to a surface
CN101425502B (zh) * 2005-03-30 2012-07-11 雅马哈株式会社 适合半导体器件的熔丝断开方法
KR101046229B1 (ko) * 2009-03-17 2011-07-04 주식회사 하이닉스반도체 퓨즈를 포함하는 반도체 장치
KR101113187B1 (ko) * 2010-01-29 2012-02-15 주식회사 하이닉스반도체 열 확산을 방지할 수 있는 전기적 퓨즈를 구비하는 반도체 집적 회로
KR101649967B1 (ko) * 2010-05-04 2016-08-23 삼성전자주식회사 이-퓨즈 구조체를 포함하는 반도체 소자 및 그 제조 방법

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE794202A (fr) * 1972-01-19 1973-05-16 Intel Corp Liaison fusible pour circuit integre sur substrat semi-conducteur pour memoires
JPS6044829B2 (ja) * 1982-03-18 1985-10-05 富士通株式会社 半導体装置の製造方法
JPS60176250A (ja) * 1984-02-23 1985-09-10 Toshiba Corp 半導体装置の製造方法
US4665295A (en) * 1984-08-02 1987-05-12 Texas Instruments Incorporated Laser make-link programming of semiconductor devices
JPS6480038A (en) * 1987-09-19 1989-03-24 Hitachi Ltd Manufacture of semiconductor integrated circuit device
JPH01107742A (ja) * 1987-10-20 1989-04-25 Fuji Photo Film Co Ltd 放射線画像診断装置
DE68906133T2 (de) * 1988-12-19 1993-10-21 Nat Semiconductor Corp Programmierbare schmelzbare Verbindungsstruktur, die Plasmametallätzen erlaubt.
JPH0352254A (ja) * 1989-07-20 1991-03-06 Toshiba Corp Ｍｏｓ型半導体装置およびその製造方法
JP2816394B2 (ja) * 1989-10-24 1998-10-27 セイコークロック株式会社 半導体装置
US5241212A (en) * 1990-05-01 1993-08-31 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a redundant circuit portion and a manufacturing method of the same
JP2656368B2 (ja) * 1990-05-08 1997-09-24 株式会社東芝 ヒューズの切断方法
US5300456A (en) * 1993-06-17 1994-04-05 Texas Instruments Incorporated Metal-to-metal antifuse structure
JPH07130861A (ja) * 1994-01-31 1995-05-19 Hitachi Ltd 半導体集積回路装置の製造方法
US5879966A (en) * 1994-09-06 1999-03-09 Taiwan Semiconductor Manufacturing Company Ltd. Method of making an integrated circuit having an opening for a fuse
US5578517A (en) * 1994-10-24 1996-11-26 Taiwan Semiconductor Manufacturing Company Ltd. Method of forming a highly transparent silicon rich nitride protective layer for a fuse window
US5550399A (en) * 1994-11-03 1996-08-27 Kabushiki Kaisha Toshiba Integrated circuit with windowed fuse element and contact pad
JPH08340049A (ja) * 1995-04-06 1996-12-24 Texas Instr Inc <Ti> 集積回路修正法
JPH08288394A (ja) * 1995-04-17 1996-11-01 Matsushita Electron Corp 半導体装置の製造方法
US5521116A (en) * 1995-04-24 1996-05-28 Texas Instruments Incorporated Sidewall formation process for a top lead fuse
EP0762498A3 (de) * 1995-08-28 1998-06-24 International Business Machines Corporation Fenster für Sicherung mit kontrollierter Sicherungsoxiddicke
JP3135039B2 (ja) * 1995-11-15 2001-02-13 日本電気株式会社 半導体装置
JPH09153552A (ja) * 1995-11-29 1997-06-10 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5895262A (en) * 1996-01-31 1999-04-20 Micron Technology, Inc. Methods for etching fuse openings in a semiconductor device
JPH09237497A (ja) * 1996-02-29 1997-09-09 Sony Corp 半導体メモリ装置
US5712206A (en) * 1996-03-20 1998-01-27 Vanguard International Semiconductor Corporation Method of forming moisture barrier layers for integrated circuit applications
US5652175A (en) * 1996-07-19 1997-07-29 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing a fuse structure
KR100192591B1 (ko) * 1996-08-22 1999-06-15 윤종용 반도체 메모리 장치의 리페어회로의 제조방법
JPH10125868A (ja) * 1996-10-23 1998-05-15 Hitachi Ltd 半導体集積回路装置およびその製造方法ならびに半導体集積回路装置の救済方法
JPH10163324A (ja) * 1996-11-29 1998-06-19 Sony Corp 半導体装置の製造方法
KR19980065743A (ko) * 1997-01-14 1998-10-15 김광호 안티 퓨즈를 구비하는 반도체장치 및 그 형성방법
JPH11260922A (ja) * 1998-03-13 1999-09-24 Toshiba Corp 半導体装置及びその製造方法
US6037648A (en) * 1998-06-26 2000-03-14 International Business Machines Corporation Semiconductor structure including a conductive fuse and process for fabrication thereof
US6121074A (en) * 1998-11-05 2000-09-19 Siemens Aktiengesellschaft Fuse layout for improved fuse blow process window

Also Published As

Publication number Publication date
US6121074A (en) 2000-09-19
TW424317B (en) 2001-03-01
CN1254941A (zh) 2000-05-31
CN1139123C (zh) 2004-02-18
JP2000150655A (ja) 2000-05-30
EP0999592A1 (de) 2000-05-10
KR20000035223A (ko) 2000-06-26
EP0999592B1 (de) 2008-09-10
JP4621319B2 (ja) 2011-01-26
KR100695591B1 (ko) 2007-03-14

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee