DE69829716D1 - Herstellungsverfahren für eingebettete Kupferleitungsverbindung - Google Patents

Herstellungsverfahren für eingebettete Kupferleitungsverbindung

Info

Publication number
DE69829716D1
DE69829716D1 DE69829716T DE69829716T DE69829716D1 DE 69829716 D1 DE69829716 D1 DE 69829716D1 DE 69829716 T DE69829716 T DE 69829716T DE 69829716 T DE69829716 T DE 69829716T DE 69829716 D1 DE69829716 D1 DE 69829716D1
Authority
DE
Germany
Prior art keywords
manufacturing
line connection
copper line
embedded copper
embedded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69829716T
Other languages
English (en)
Other versions
DE69829716T2 (de
Inventor
Naoaki Ogure
Hiroaki Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ebara Corp
Original Assignee
Ebara Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ebara Corp filed Critical Ebara Corp
Publication of DE69829716D1 publication Critical patent/DE69829716D1/de
Application granted granted Critical
Publication of DE69829716T2 publication Critical patent/DE69829716T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
DE69829716T 1997-09-18 1998-09-18 Verfahren zum Ausbilden eingebetteter Kupferzwischenverbindungen und eingebettete Kupferzwischenverbindungsstruktur Expired - Fee Related DE69829716T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP27200197A JP3545177B2 (ja) 1997-09-18 1997-09-18 多層埋め込みＣｕ配線形成方法
JP27200197 1997-09-18

Publications (2)

Publication Number Publication Date
DE69829716D1 true DE69829716D1 (de) 2005-05-19
DE69829716T2 DE69829716T2 (de) 2006-03-09

Family

ID=17507772

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69829716T Expired - Fee Related DE69829716T2 (de) 1997-09-18 1998-09-18 Verfahren zum Ausbilden eingebetteter Kupferzwischenverbindungen und eingebettete Kupferzwischenverbindungsstruktur

Country Status (5)

Country Link
US (3) US6147408A (de)
EP (2) EP1471572A1 (de)
JP (1) JP3545177B2 (de)
KR (1) KR100555931B1 (de)
DE (1) DE69829716T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6214728B1 (en) * 1998-11-20 2001-04-10 Chartered Semiconductor Manufacturing, Ltd. Method to encapsulate copper plug for interconnect metallization
US6444567B1 (en) * 2000-01-05 2002-09-03 Advanced Micro Devices, Inc. Process for alloying damascene-type Cu interconnect lines
US6455424B1 (en) * 2000-08-07 2002-09-24 Micron Technology, Inc. Selective cap layers over recessed polysilicon plugs
CN1329972C (zh) * 2001-08-13 2007-08-01 株式会社荏原制作所 半导体器件及其制造方法
US6709971B2 (en) * 2002-01-30 2004-03-23 Intel Corporation Interconnect structures in a semiconductor device and processes of formation
US7045861B2 (en) * 2002-03-26 2006-05-16 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device, liquid-crystal display device and method for manufacturing same
US20030227091A1 (en) * 2002-06-06 2003-12-11 Nishant Sinha Plating metal caps on conductive interconnect for wirebonding
JP2004039916A (ja) * 2002-07-04 2004-02-05 Nec Electronics Corp 半導体装置およびその製造方法
US7229922B2 (en) * 2003-10-27 2007-06-12 Intel Corporation Method for making a semiconductor device having increased conductive material reliability
US7268074B2 (en) * 2004-06-14 2007-09-11 Enthone, Inc. Capping of metal interconnects in integrated circuit electronic devices
JP4275644B2 (ja) 2004-06-23 2009-06-10 シャープ株式会社 アクティブマトリクス基板およびその製造方法、並びに電子装置
CN101137933A (zh) * 2005-03-11 2008-03-05 Lg化学株式会社 具有银覆盖的电极的lcd器件
DE102007035837A1 (de) * 2007-07-31 2009-02-05 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit einer Kornorientierungsschicht
US8586472B2 (en) * 2010-07-14 2013-11-19 Infineon Technologies Ag Conductive lines and pads and method of manufacturing thereof
US9087777B2 (en) * 2013-03-14 2015-07-21 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996584A (en) * 1985-01-31 1991-02-26 Gould, Inc. Thin-film electrical connections for integrated circuits
US4619887A (en) * 1985-09-13 1986-10-28 Texas Instruments Incorporated Method of plating an interconnect metal onto a metal in VLSI devices
JPH0815152B2 (ja) * 1986-01-27 1996-02-14 三菱電機株式会社 半導体装置及びその製造方法
JPS63100749A (ja) * 1986-10-17 1988-05-02 Hitachi Ltd 半導体集積回路装置
JP2624703B2 (ja) * 1987-09-24 1997-06-25 株式会社東芝 バンプの形成方法及びその装置
US5071518A (en) * 1989-10-24 1991-12-10 Microelectronics And Computer Technology Corporation Method of making an electrical multilayer interconnect
US5098860A (en) 1990-05-07 1992-03-24 The Boeing Company Method of fabricating high-density interconnect structures having tantalum/tantalum oxide layers
JP2609940B2 (ja) * 1990-06-22 1997-05-14 鐘淵化学工業株式会社 多層配線体
JPH04209576A (ja) * 1990-12-07 1992-07-30 Kanegafuchi Chem Ind Co Ltd 光電変換素子
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
JPH066012A (ja) * 1992-06-16 1994-01-14 Ebara Corp 電気回路の被覆構造
US5406120A (en) * 1992-10-20 1995-04-11 Jones; Robert M. Hermetically sealed semiconductor ceramic package
JP3049161B2 (ja) * 1992-11-18 2000-06-05 イビデン株式会社 マルチチップ薄膜多層配線板の製造方法
DE4400200C2 (de) * 1993-01-05 1997-09-04 Toshiba Kawasaki Kk Halbleitervorrichtung mit verbesserter Verdrahtungsstruktur und Verfahren zu ihrer Herstellung
JPH08148563A (ja) * 1994-11-22 1996-06-07 Nec Corp 半導体装置の多層配線構造体の形成方法
US5545927A (en) 1995-05-12 1996-08-13 International Business Machines Corporation Capped copper electrical interconnects
US5549808A (en) 1995-05-12 1996-08-27 International Business Machines Corporation Method for forming capped copper electrical interconnects
US5674787A (en) * 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications
US5913147A (en) 1997-01-21 1999-06-15 Advanced Micro Devices, Inc. Method for fabricating copper-aluminum metallization
US5939334A (en) * 1997-05-22 1999-08-17 Sharp Laboratories Of America, Inc. System and method of selectively cleaning copper substrate surfaces, in-situ, to remove copper oxides
US6069068A (en) 1997-05-30 2000-05-30 International Business Machines Corporation Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity
US5891802A (en) * 1997-07-23 1999-04-06 Advanced Micro Devices, Inc. Method for fabricating a metallization stack structure to improve electromigration resistance and keep low resistivity of ULSI interconnects
US6214728B1 (en) * 1998-11-20 2001-04-10 Chartered Semiconductor Manufacturing, Ltd. Method to encapsulate copper plug for interconnect metallization
US6309964B1 (en) 1999-07-08 2001-10-30 Taiwan Semiconductor Manufacturing Company Method for forming a copper damascene structure over tungsten plugs with improved adhesion, oxidation resistance, and diffusion barrier properties using nitridation of the tungsten plug
US6114243A (en) * 1999-11-15 2000-09-05 Chartered Semiconductor Manufacturing Ltd Method to avoid copper contamination on the sidewall of a via or a dual damascene structure
US6274499B1 (en) * 1999-11-19 2001-08-14 Chartered Semiconductor Manufacturing Ltd. Method to avoid copper contamination during copper etching and CMP
US6291082B1 (en) * 2000-06-13 2001-09-18 Advanced Micro Devices, Inc. Method of electroless ag layer formation for cu interconnects

Also Published As

Publication number Publication date
EP0903781B1 (de) 2005-04-13
EP1471572A1 (de) 2004-10-27
DE69829716T2 (de) 2006-03-09
JP3545177B2 (ja) 2004-07-21
US6147408A (en) 2000-11-14
EP0903781A2 (de) 1999-03-24
JPH1197441A (ja) 1999-04-09
US6787467B2 (en) 2004-09-07
EP0903781A3 (de) 1999-07-21
US6391775B1 (en) 2002-05-21
KR100555931B1 (ko) 2006-05-03
KR19990029869A (ko) 1999-04-26
US20020111022A1 (en) 2002-08-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee