DE69840861D1 - Verfahren zum Oxidieren einer Struktur während der Herstellung einer Halbleitervorrichtung - Google Patents

Verfahren zum Oxidieren einer Struktur während der Herstellung einer Halbleitervorrichtung

Info

Publication number
DE69840861D1
DE69840861D1 DE69840861T DE69840861T DE69840861D1 DE 69840861 D1 DE69840861 D1 DE 69840861D1 DE 69840861 T DE69840861 T DE 69840861T DE 69840861 T DE69840861 T DE 69840861T DE 69840861 D1 DE69840861 D1 DE 69840861D1
Authority
DE
Germany
Prior art keywords
oxidizing
manufacture
semiconductor device
structure during
during
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69840861T
Other languages
English (en)
Inventor
Boyang Lin
Ming Hwang
Takayuki Niuya
Song Park
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69840861D1 publication Critical patent/DE69840861D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32105Oxidation of silicon-containing layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69840861T 1997-10-14 1998-10-13 Verfahren zum Oxidieren einer Struktur während der Herstellung einer Halbleitervorrichtung Expired - Lifetime DE69840861D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US6182797P 1997-10-14 1997-10-14

Publications (1)

Publication Number Publication Date
DE69840861D1 true DE69840861D1 (de) 2009-07-16

Family

ID=22038390

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69840861T Expired - Lifetime DE69840861D1 (de) 1997-10-14 1998-10-13 Verfahren zum Oxidieren einer Struktur während der Herstellung einer Halbleitervorrichtung

Country Status (3)

Country Link
EP (2) EP2063464B1 (de)
JP (1) JPH11238702A (de)
DE (1) DE69840861D1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6534401B2 (en) 2000-04-27 2003-03-18 Applied Materials, Inc. Method for selectively oxidizing a silicon/metal composite film stack
JP4801248B2 (ja) * 2000-10-31 2011-10-26 アプライド マテリアルズ インコーポレイテッド 酸化膜形成方法及び装置
US6638877B2 (en) * 2000-11-03 2003-10-28 Texas Instruments Incorporated Ultra-thin SiO2using N2O as the oxidant
JP4706260B2 (ja) * 2004-02-25 2011-06-22 東京エレクトロン株式会社 被処理体の酸化方法、酸化装置及び記憶媒体
US7951728B2 (en) * 2007-09-24 2011-05-31 Applied Materials, Inc. Method of improving oxide growth rate of selective oxidation processes

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59132136A (ja) * 1983-01-19 1984-07-30 Hitachi Ltd 半導体装置の製造方法
JPS609166A (ja) * 1983-06-29 1985-01-18 Hitachi Ltd 半導体装置の製造方法
JPS60134441A (ja) * 1983-12-23 1985-07-17 Hitachi Ltd 半導体装置
JPS60250630A (ja) * 1984-05-28 1985-12-11 Hitachi Ltd 半導体装置の製造方法
JPH04328862A (ja) * 1991-04-30 1992-11-17 Hitachi Ltd 半導体集積回路装置の製造方法
US5257926A (en) * 1991-12-17 1993-11-02 Gideon Drimer Fast, safe, pyrogenic external torch assembly
JP3207943B2 (ja) * 1992-11-17 2001-09-10 忠弘 大見 低温酸化膜形成装置および低温酸化膜形成方法
JPH0766408A (ja) * 1993-08-31 1995-03-10 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0910119B1 (de) 2009-06-03
EP2063464A3 (de) 2009-06-17
JPH11238702A (ja) 1999-08-31
EP2063464A2 (de) 2009-05-27
EP0910119A3 (de) 2001-02-07
EP0910119A2 (de) 1999-04-21
EP2063464B1 (de) 2017-11-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition