DE69736499D1 - Montageverfahren für eine Mehrzahl von Halbleiteranordnungen in korrespondierenden Trägern - Google Patents

Montageverfahren für eine Mehrzahl von Halbleiteranordnungen in korrespondierenden Trägern

Info

Publication number
DE69736499D1
DE69736499D1 DE69736499T DE69736499T DE69736499D1 DE 69736499 D1 DE69736499 D1 DE 69736499D1 DE 69736499 T DE69736499 T DE 69736499T DE 69736499 T DE69736499 T DE 69736499T DE 69736499 D1 DE69736499 D1 DE 69736499D1
Authority
DE
Germany
Prior art keywords
semiconductor devices
assembly method
corresponding carriers
carriers
assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69736499T
Other languages
English (en)
Other versions
DE69736499T2 (de
Inventor
Sumie Sato
Jun Ohmori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69736499D1 publication Critical patent/DE69736499D1/de
Application granted granted Critical
Publication of DE69736499T2 publication Critical patent/DE69736499T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
  • Die Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Dicing (AREA)
DE69736499T 1996-04-25 1997-04-22 Montageverfahren für eine Mehrzahl von Halbleiteranordnungen in korrespondierenden Trägern Expired - Lifetime DE69736499T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10535996 1996-04-25
JP10535996 1996-04-25

Publications (2)

Publication Number Publication Date
DE69736499D1 true DE69736499D1 (de) 2006-09-28
DE69736499T2 DE69736499T2 (de) 2007-08-16

Family

ID=14405537

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69736499T Expired - Lifetime DE69736499T2 (de) 1996-04-25 1997-04-22 Montageverfahren für eine Mehrzahl von Halbleiteranordnungen in korrespondierenden Trägern

Country Status (6)

Country Link
US (1) US5956601A (de)
EP (1) EP0803901B1 (de)
KR (1) KR100269850B1 (de)
CN (1) CN1092399C (de)
DE (1) DE69736499T2 (de)
TW (1) TW334619B (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
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FR2773900B1 (fr) * 1998-01-22 2000-02-18 Gemplus Card Int Carte a circuit(s) integre(s) a contact, comportant une minicarte detachable
SG80077A1 (en) * 1998-10-19 2001-04-17 Sony Corp Semiconductor integrated circuit card manufacturing method, and semiconductor integrated circuit card
AU2001263463A1 (en) 2000-06-06 2001-12-17 Sawtek, Inc. System and method for array processing of surface acoustic wave devices
JP2002092575A (ja) * 2000-09-19 2002-03-29 Mitsubishi Electric Corp 小型カードとその製造方法
JP4162930B2 (ja) * 2002-06-25 2008-10-08 富士機械製造株式会社 電子部品実装装置における基板搬送装置
JP4002143B2 (ja) * 2002-07-10 2007-10-31 株式会社ルネサステクノロジ 半導体装置の製造方法
CN100336072C (zh) * 2004-06-16 2007-09-05 台湾典范半导体股份有限公司 记忆卡的构装方法及其结构
USD794641S1 (en) * 2009-01-07 2017-08-15 Samsung Electronics Co., Ltd. Memory device
USD794643S1 (en) * 2009-01-07 2017-08-15 Samsung Electronics Co., Ltd. Memory device
USD794644S1 (en) * 2009-01-07 2017-08-15 Samsung Electronics Co., Ltd. Memory device
USD795261S1 (en) * 2009-01-07 2017-08-22 Samsung Electronics Co., Ltd. Memory device
USD795262S1 (en) * 2009-01-07 2017-08-22 Samsung Electronics Co., Ltd. Memory device
USD794034S1 (en) * 2009-01-07 2017-08-08 Samsung Electronics Co., Ltd. Memory device
USD794642S1 (en) * 2009-01-07 2017-08-15 Samsung Electronics Co., Ltd. Memory device
CN111640677B (zh) * 2020-03-02 2022-04-26 浙江集迈科微电子有限公司 一种凹槽内芯片放置方法

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JP2582013B2 (ja) * 1991-02-08 1997-02-19 株式会社東芝 樹脂封止型半導体装置及びその製造方法
IT1212711B (it) * 1983-03-09 1989-11-30 Ates Componenti Elettron Dispositivo a semiconduttore aforma di scheda piana con contatti elettrici su ambedue le facce eprocedimento per la sua fabbricazione.
FR2580416B1 (fr) * 1985-04-12 1987-06-05 Radiotechnique Compelec Procede et dispositif pour fabriquer une carte d'identification electronique
DE3546780C2 (de) * 1985-09-02 1996-04-25 Amphenol Corp Kontaktiereinrichtung für eine Chipkarte
JPS6478397A (en) * 1987-09-18 1989-03-23 Mitsubishi Electric Corp Ic card writing system
FR2624635B1 (fr) * 1987-12-14 1991-05-10 Sgs Thomson Microelectronics Support de composant electronique pour carte memoire et produit ainsi obtenu
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US5068714A (en) * 1989-04-05 1991-11-26 Robert Bosch Gmbh Method of electrically and mechanically connecting a semiconductor to a substrate using an electrically conductive tacky adhesive and the device so made
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Also Published As

Publication number Publication date
EP0803901A3 (de) 1999-09-22
EP0803901A2 (de) 1997-10-29
KR100269850B1 (ko) 2000-10-16
TW334619B (en) 1998-06-21
CN1092399C (zh) 2002-10-09
EP0803901B1 (de) 2006-08-16
US5956601A (en) 1999-09-21
DE69736499T2 (de) 2007-08-16
CN1173041A (zh) 1998-02-11

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