DE69725632D1 - Halbleiterspeicheranordnung mit "Pipeline" Betrieb - Google Patents

Halbleiterspeicheranordnung mit "Pipeline" Betrieb

Info

Publication number
DE69725632D1
DE69725632D1 DE69725632T DE69725632T DE69725632D1 DE 69725632 D1 DE69725632 D1 DE 69725632D1 DE 69725632 T DE69725632 T DE 69725632T DE 69725632 T DE69725632 T DE 69725632T DE 69725632 D1 DE69725632 D1 DE 69725632D1
Authority
DE
Germany
Prior art keywords
pipeline
semiconductor memory
memory arrangement
arrangement
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69725632T
Other languages
English (en)
Other versions
DE69725632T2 (de
Inventor
Yoshinori Okajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69725632D1 publication Critical patent/DE69725632D1/de
Application granted granted Critical
Publication of DE69725632T2 publication Critical patent/DE69725632T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
DE69725632T 1996-02-02 1997-01-30 Halbleiterspeicheranordnung mit "Pipeline" Betrieb Expired - Lifetime DE69725632T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1799096 1996-02-02
JP01799096A JP4084428B2 (ja) 1996-02-02 1996-02-02 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69725632D1 true DE69725632D1 (de) 2003-11-27
DE69725632T2 DE69725632T2 (de) 2004-06-17

Family

ID=11959169

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69725632T Expired - Lifetime DE69725632T2 (de) 1996-02-02 1997-01-30 Halbleiterspeicheranordnung mit "Pipeline" Betrieb

Country Status (6)

Country Link
US (3) US6163832A (de)
EP (1) EP0788110B1 (de)
JP (1) JP4084428B2 (de)
KR (1) KR100267962B1 (de)
DE (1) DE69725632T2 (de)
TW (1) TW332294B (de)

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US6178488B1 (en) 1998-08-27 2001-01-23 Micron Technology, Inc. Method and apparatus for processing pipelined memory commands
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US6748442B1 (en) * 1998-12-21 2004-06-08 Advanced Micro Devices, Inc. Method and apparatus for using a control signal on a packet based communication link
DE69942620D1 (de) 1999-06-10 2010-09-02 Belle Gate Invest B V Vorrichtung zum speichern unterschiedlicher versionen von datensätzen in getrennten datenbereichen uin einem speicher
US6708248B1 (en) * 1999-07-23 2004-03-16 Rambus Inc. Memory system with channel multiplexing of multiple memory devices
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BR9917574A (pt) 1999-12-07 2002-08-06 Sun Microsystems Inc Meio legìvel por computador com microprocessador para controlar a leitura e computador disposto para se comunicar com tal meio
WO2001042929A1 (en) * 1999-12-08 2001-06-14 Rambus Inc Memory system with channel multiplexing of multiple memory devices
US7012613B1 (en) 2000-05-02 2006-03-14 Ati International Srl Method and apparatus for fragment scriptor for use in over-sampling anti-aliasing
AU2001270400A1 (en) * 2000-07-07 2002-01-21 Mosaid Technologies Incorporated A high speed dram architecture with uniform access latency
CA2416844A1 (en) 2000-07-20 2002-01-31 Belle Gate Investment B.V. Method and system of communicating devices, and devices therefor, with protected data transfer
US6900812B1 (en) * 2000-08-02 2005-05-31 Ati International Srl Logic enhanced memory and method therefore
KR100401490B1 (ko) * 2000-10-31 2003-10-11 주식회사 하이닉스반도체 로오 버퍼를 내장한 반도체 메모리 장치
DE10059553B4 (de) * 2000-11-30 2005-04-28 Infineon Technologies Ag Schaltungsanordnung und Verfahren zum Synchronisieren
US6557090B2 (en) * 2001-03-09 2003-04-29 Micron Technology, Inc. Column address path circuit and method for memory devices having a burst access mode
US6622203B2 (en) * 2001-05-29 2003-09-16 Agilent Technologies, Inc. Embedded memory access method and system for application specific integrated circuits
DE10164338A1 (de) * 2001-12-28 2003-07-17 Thomson Brandt Gmbh Verfahren zur Einstellung eines Betriebsparameters in einem Peripherie-IC und Vorrichtung zur Durchführung des Verfahrens
US6829184B2 (en) * 2002-01-28 2004-12-07 Intel Corporation Apparatus and method for encoding auto-precharge
US6721227B2 (en) * 2002-02-11 2004-04-13 Micron Technology, Inc. User selectable banks for DRAM
US20030163654A1 (en) * 2002-02-22 2003-08-28 Eliel Louzoun System and method for efficient scheduling of memory
KR100452328B1 (ko) * 2002-07-31 2004-10-12 삼성전자주식회사 동기식 반도체 메모리 장치의 데이터 출력회로
KR100505109B1 (ko) * 2003-03-26 2005-07-29 삼성전자주식회사 읽기 시간을 단축시킬 수 있는 플래시 메모리 장치
US7496753B2 (en) * 2004-09-02 2009-02-24 International Business Machines Corporation Data encryption interface for reducing encrypt latency impact on standard traffic
US7409558B2 (en) * 2004-09-02 2008-08-05 International Business Machines Corporation Low-latency data decryption interface
KR100649834B1 (ko) * 2004-10-22 2006-11-28 주식회사 하이닉스반도체 반도체 메모리 소자의 누설 전류 제어 장치
DE102006053072B4 (de) * 2006-11-10 2014-09-04 Qimonda Ag Verfahren zum Auslesen von Datenpaketen
KR100856069B1 (ko) * 2007-03-29 2008-09-02 주식회사 하이닉스반도체 반도체 메모리 장치 및 그의 구동방법
US8006032B2 (en) * 2007-08-22 2011-08-23 Globalfoundries Inc. Optimal solution to control data channels
US7787311B2 (en) * 2007-11-08 2010-08-31 Rao G R Mohan Memory with programmable address strides for accessing and precharging during the same access cycle
US9978437B2 (en) * 2015-12-11 2018-05-22 Micron Technology, Inc. Apparatuses and methods for dynamic voltage and frequency switching for dynamic random access memory
WO2017191706A1 (ja) * 2016-05-02 2017-11-09 ソニー株式会社 メモリ制御回路、メモリ、記憶装置、および、情報処理システム
KR102576767B1 (ko) * 2018-12-03 2023-09-12 에스케이하이닉스 주식회사 반도체장치
CN110941395B (zh) * 2019-11-15 2023-06-16 深圳宏芯宇电子股份有限公司 动态随机存取存储器、内存管理方法、系统及存储介质

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Also Published As

Publication number Publication date
US6055615A (en) 2000-04-25
EP0788110B1 (de) 2003-10-22
TW332294B (en) 1998-05-21
US6163832A (en) 2000-12-19
EP0788110A2 (de) 1997-08-06
KR100267962B1 (ko) 2000-10-16
KR970063250A (ko) 1997-09-12
JPH09213068A (ja) 1997-08-15
JP4084428B2 (ja) 2008-04-30
EP0788110A3 (de) 1999-02-03
DE69725632T2 (de) 2004-06-17
US6507900B1 (en) 2003-01-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE