DE69717572T2 - Halbleiterspeicheranordnung mit erhöhter Bandbreite - Google Patents
Halbleiterspeicheranordnung mit erhöhter BandbreiteInfo
- Publication number
- DE69717572T2 DE69717572T2 DE69717572T DE69717572T DE69717572T2 DE 69717572 T2 DE69717572 T2 DE 69717572T2 DE 69717572 T DE69717572 T DE 69717572T DE 69717572 T DE69717572 T DE 69717572T DE 69717572 T2 DE69717572 T2 DE 69717572T2
- Authority
- DE
- Germany
- Prior art keywords
- memory device
- semiconductor memory
- increased bandwidth
- bandwidth
- increased
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24490496A JP3291206B2 (ja) | 1996-09-17 | 1996-09-17 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69717572D1 DE69717572D1 (de) | 2003-01-16 |
DE69717572T2 true DE69717572T2 (de) | 2003-04-10 |
Family
ID=17125703
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69717572T Expired - Lifetime DE69717572T2 (de) | 1996-09-17 | 1997-02-21 | Halbleiterspeicheranordnung mit erhöhter Bandbreite |
Country Status (6)
Country | Link |
---|---|
US (1) | US5838604A (de) |
EP (1) | EP0829880B1 (de) |
JP (1) | JP3291206B2 (de) |
KR (1) | KR100235144B1 (de) |
DE (1) | DE69717572T2 (de) |
TW (1) | TW315470B (de) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3085241B2 (ja) * | 1997-04-11 | 2000-09-04 | 日本電気株式会社 | 半導体記憶装置 |
JP3992781B2 (ja) * | 1997-04-15 | 2007-10-17 | 富士通株式会社 | 半導体記憶装置 |
JP3933769B2 (ja) * | 1997-10-20 | 2007-06-20 | 富士通株式会社 | 半導体記憶装置 |
US5936877A (en) | 1998-02-13 | 1999-08-10 | Micron Technology, Inc. | Die architecture accommodating high-speed semiconductor devices |
JP3248617B2 (ja) | 1998-07-14 | 2002-01-21 | 日本電気株式会社 | 半導体記憶装置 |
FR2784219B1 (fr) * | 1998-09-16 | 2001-11-02 | St Microelectronics Sa | Architecture de circuit memoire |
JP2000100156A (ja) | 1998-09-25 | 2000-04-07 | Fujitsu Ltd | 半導体記憶装置のセル情報書き込み方法及び半導体記憶装置 |
JP2000182390A (ja) * | 1998-12-11 | 2000-06-30 | Mitsubishi Electric Corp | 半導体記憶装置 |
TW462055B (en) * | 1999-04-28 | 2001-11-01 | Fujitsu Ltd | Semiconductor memory device |
JP3856596B2 (ja) * | 1999-05-28 | 2006-12-13 | 富士通株式会社 | 半導体記憶装置 |
DE10104265B4 (de) * | 2001-01-31 | 2008-09-25 | Qimonda Ag | Verfahren zum Herstellen einer Halbleiterschaltungsanordnung |
JP4326226B2 (ja) * | 2003-01-20 | 2009-09-02 | Okiセミコンダクタ株式会社 | 半導体集積回路 |
US20080203092A1 (en) * | 2007-02-28 | 2008-08-28 | Stamper Leonard R | Container sealing system |
KR101591940B1 (ko) * | 2009-04-23 | 2016-02-05 | 삼성전자주식회사 | 비휘발성 메모리 장치 |
JP2012128921A (ja) * | 2010-12-17 | 2012-07-05 | Toshiba Corp | 半導体記憶装置 |
JP5827145B2 (ja) | 2011-03-08 | 2015-12-02 | 株式会社半導体エネルギー研究所 | 信号処理回路 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62231495A (ja) * | 1986-03-31 | 1987-10-12 | Toshiba Corp | 半導体記憶装置 |
US5062079A (en) * | 1988-09-28 | 1991-10-29 | Kabushiki Kaisha Toshiba | MOS type random access memory with interference noise eliminator |
JPH02246087A (ja) * | 1989-03-20 | 1990-10-01 | Hitachi Ltd | 半導体記憶装置ならびにその冗長方式及びレイアウト方式 |
US5261068A (en) * | 1990-05-25 | 1993-11-09 | Dell Usa L.P. | Dual path memory retrieval system for an interleaved dynamic RAM memory unit |
JP2611504B2 (ja) * | 1990-06-15 | 1997-05-21 | 日本電気株式会社 | 半導体メモリ |
US5325336A (en) * | 1992-09-10 | 1994-06-28 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having power line arranged in a meshed shape |
JP2725570B2 (ja) * | 1993-11-02 | 1998-03-11 | 日本電気株式会社 | 半導体メモリ装置 |
JPH08172169A (ja) * | 1994-12-16 | 1996-07-02 | Toshiba Microelectron Corp | 半導体記憶装置 |
US5535172A (en) * | 1995-02-28 | 1996-07-09 | Alliance Semiconductor Corporation | Dual-port random access memory having reduced architecture |
JP3386924B2 (ja) * | 1995-05-22 | 2003-03-17 | 株式会社日立製作所 | 半導体装置 |
KR0186094B1 (ko) * | 1995-10-12 | 1999-05-15 | 구본준 | 메모리 소자내의 메인앰프의 배치구조 |
US5687108A (en) * | 1996-04-10 | 1997-11-11 | Proebsting; Robert J. | Power bussing layout for memory circuits |
-
1996
- 1996-09-17 JP JP24490496A patent/JP3291206B2/ja not_active Expired - Fee Related
-
1997
- 1997-02-20 US US08/803,448 patent/US5838604A/en not_active Expired - Lifetime
- 1997-02-21 DE DE69717572T patent/DE69717572T2/de not_active Expired - Lifetime
- 1997-02-21 EP EP97301157A patent/EP0829880B1/de not_active Expired - Lifetime
- 1997-02-26 TW TW086102330A patent/TW315470B/zh not_active IP Right Cessation
- 1997-02-27 KR KR1019970006145A patent/KR100235144B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TW315470B (en) | 1997-09-11 |
EP0829880A2 (de) | 1998-03-18 |
JPH1092177A (ja) | 1998-04-10 |
KR19980023953A (ko) | 1998-07-06 |
KR100235144B1 (ko) | 1999-12-15 |
EP0829880B1 (de) | 2002-12-04 |
JP3291206B2 (ja) | 2002-06-10 |
DE69717572D1 (de) | 2003-01-16 |
EP0829880A3 (de) | 1999-05-12 |
US5838604A (en) | 1998-11-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP |
|
8328 | Change in the person/name/address of the agent |
Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE |