DE69619793T2 - Halbleiterspeicheranordnung mit Haupt- und Nebenbitleitungsanordnung - Google Patents

Halbleiterspeicheranordnung mit Haupt- und Nebenbitleitungsanordnung

Info

Publication number
DE69619793T2
DE69619793T2 DE69619793T DE69619793T DE69619793T2 DE 69619793 T2 DE69619793 T2 DE 69619793T2 DE 69619793 T DE69619793 T DE 69619793T DE 69619793 T DE69619793 T DE 69619793T DE 69619793 T2 DE69619793 T2 DE 69619793T2
Authority
DE
Germany
Prior art keywords
arrangement
main
bit line
semiconductor memory
secondary bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69619793T
Other languages
English (en)
Other versions
DE69619793D1 (de
Inventor
Tadahiko Sugibayashi
Isao Naritake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69619793D1 publication Critical patent/DE69619793D1/de
Application granted granted Critical
Publication of DE69619793T2 publication Critical patent/DE69619793T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
DE69619793T 1995-09-14 1996-09-12 Halbleiterspeicheranordnung mit Haupt- und Nebenbitleitungsanordnung Expired - Fee Related DE69619793T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7236508A JP2900854B2 (ja) 1995-09-14 1995-09-14 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69619793D1 DE69619793D1 (de) 2002-04-18
DE69619793T2 true DE69619793T2 (de) 2002-11-21

Family

ID=17001763

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69619793T Expired - Fee Related DE69619793T2 (de) 1995-09-14 1996-09-12 Halbleiterspeicheranordnung mit Haupt- und Nebenbitleitungsanordnung

Country Status (6)

Country Link
US (1) US5732026A (de)
EP (1) EP0791932B1 (de)
JP (1) JP2900854B2 (de)
KR (1) KR100225826B1 (de)
DE (1) DE69619793T2 (de)
TW (1) TW360972B (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6009024A (en) * 1997-03-27 1999-12-28 Matsushita Electric Industrial Co., Ltd. Semiconductor memory
JPH11110967A (ja) * 1997-10-01 1999-04-23 Nec Corp 半導体メモリ装置
JP2000090659A (ja) * 1998-09-10 2000-03-31 Nec Corp 半導体記憶装置
KR100487918B1 (ko) * 2002-08-30 2005-05-09 주식회사 하이닉스반도체 불휘발성 강유전체 메모리 장치
US7349266B2 (en) * 2004-06-10 2008-03-25 Freescale Semiconductor, Inc. Memory device with a data hold latch
US7289369B2 (en) * 2005-04-18 2007-10-30 International Business Machines Corporation DRAM hierarchical data path
US7719905B2 (en) * 2007-05-17 2010-05-18 Hynix Semiconductor, Inc. Semiconductor memory device
US9053817B2 (en) * 2013-03-15 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Amplifier
US11798613B2 (en) 2018-12-10 2023-10-24 Etron Technology, Inc. Dynamic memory with long retention time
US11302383B2 (en) 2018-12-10 2022-04-12 Etron Technology, Inc. Dynamic memory with sustainable storage architecture

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4344156A (en) * 1980-10-10 1982-08-10 Inmos Corporation High speed data transfer for a semiconductor memory
US4943944A (en) * 1987-11-25 1990-07-24 Kabushiki Kaisha Toshiba Semiconductor memory using dynamic ram cells
JP2713929B2 (ja) * 1987-11-25 1998-02-16 株式会社東芝 半導体記憶装置
JP2579974B2 (ja) * 1987-11-25 1997-02-12 株式会社東芝 半導体記憶装置
JP2591010B2 (ja) * 1988-01-29 1997-03-19 日本電気株式会社 シリアルアクセスメモリ装置
JP2611504B2 (ja) * 1990-06-15 1997-05-21 日本電気株式会社 半導体メモリ
JPH06203552A (ja) * 1991-11-18 1994-07-22 Toshiba Corp ダイナミック型半導体記憶装置
JPH05250875A (ja) * 1992-02-27 1993-09-28 Nec Corp 半導体記憶装置

Also Published As

Publication number Publication date
KR970017610A (ko) 1997-04-30
JPH0982086A (ja) 1997-03-28
EP0791932A3 (de) 1998-01-14
TW360972B (en) 1999-06-11
JP2900854B2 (ja) 1999-06-02
US5732026A (en) 1998-03-24
KR100225826B1 (ko) 1999-10-15
EP0791932B1 (de) 2002-03-13
EP0791932A2 (de) 1997-08-27
DE69619793D1 (de) 2002-04-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee