DE69536143D1 - Speicherzelle und Wortleitungtreiber für einen eingebetteten DRAM-Speicher im ASIC-Herstellungsverfahren - Google Patents
Speicherzelle und Wortleitungtreiber für einen eingebetteten DRAM-Speicher im ASIC-HerstellungsverfahrenInfo
- Publication number
- DE69536143D1 DE69536143D1 DE69536143T DE69536143T DE69536143D1 DE 69536143 D1 DE69536143 D1 DE 69536143D1 DE 69536143 T DE69536143 T DE 69536143T DE 69536143 T DE69536143 T DE 69536143T DE 69536143 D1 DE69536143 D1 DE 69536143D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing process
- word line
- line driver
- embedded dram
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/355,956 US5600598A (en) | 1994-12-14 | 1994-12-14 | Memory cell and wordline driver for embedded DRAM in ASIC process |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69536143D1 true DE69536143D1 (de) | 2011-04-07 |
Family
ID=23399483
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69531090T Expired - Lifetime DE69531090T2 (de) | 1994-12-14 | 1995-12-08 | Speicherzelle und Wortleitungstreiber für ASIC-hergestellten integrierten DRAM-Speicher |
DE69536143T Expired - Lifetime DE69536143D1 (de) | 1994-12-14 | 1995-12-08 | Speicherzelle und Wortleitungtreiber für einen eingebetteten DRAM-Speicher im ASIC-Herstellungsverfahren |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69531090T Expired - Lifetime DE69531090T2 (de) | 1994-12-14 | 1995-12-08 | Speicherzelle und Wortleitungstreiber für ASIC-hergestellten integrierten DRAM-Speicher |
Country Status (4)
Country | Link |
---|---|
US (2) | US5600598A (de) |
EP (2) | EP1336970B1 (de) |
JP (1) | JP3182067B2 (de) |
DE (2) | DE69531090T2 (de) |
Families Citing this family (50)
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US20050036363A1 (en) * | 1996-05-24 | 2005-02-17 | Jeng-Jye Shau | High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines |
US5748547A (en) * | 1996-05-24 | 1998-05-05 | Shau; Jeng-Jye | High performance semiconductor memory devices having multiple dimension bit lines |
US5835438A (en) * | 1996-12-24 | 1998-11-10 | Mosaid Technologies Incorporated | Precharge-enable self boosting word line driver for an embedded DRAM |
US6136677A (en) * | 1997-09-25 | 2000-10-24 | Siemens Aktiengesellschaft | Method of fabricating semiconductor chips with silicide and implanted junctions |
US5907511A (en) * | 1997-12-23 | 1999-05-25 | Lsi Logic Corporation | Electrically selectable redundant components for an embedded DRAM |
US5896331A (en) * | 1997-12-23 | 1999-04-20 | Lsi Logic Corporation | Reprogrammable addressing process for embedded DRAM |
US6034433A (en) * | 1997-12-23 | 2000-03-07 | Intel Corporation | Interconnect structure for protecting a transistor gate from charge damage |
US6180998B1 (en) | 1998-03-30 | 2001-01-30 | Lsi Logic Corporation | DRAM with built-in noise protection |
US6064588A (en) * | 1998-03-30 | 2000-05-16 | Lsi Logic Corporation | Embedded dram with noise-protected differential capacitor memory cells |
US5999440A (en) * | 1998-03-30 | 1999-12-07 | Lsi Logic Corporation | Embedded DRAM with noise-protecting substrate isolation well |
US5973952A (en) * | 1998-03-30 | 1999-10-26 | Lsi Logic Corporation | Embedded DRAM with noise protecting shielding conductor |
US6005824A (en) * | 1998-06-30 | 1999-12-21 | Lsi Logic Corporation | Inherently compensated clocking circuit for dynamic random access memory |
US6468855B2 (en) | 1998-08-14 | 2002-10-22 | Monolithic System Technology, Inc. | Reduced topography DRAM cell fabricated using a modified logic process and method for operating same |
US6573548B2 (en) | 1998-08-14 | 2003-06-03 | Monolithic System Technology, Inc. | DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same |
US6075720A (en) * | 1998-08-14 | 2000-06-13 | Monolithic System Tech Inc | Memory cell for DRAM embedded in logic |
US6509595B1 (en) | 1999-06-14 | 2003-01-21 | Monolithic System Technology, Inc. | DRAM cell fabricated using a modified logic process and method for operating same |
US6087690A (en) * | 1998-10-13 | 2000-07-11 | Worldwide Semiconductor Manufacturing Corporation | Single polysilicon DRAM cell with current gain |
US6136638A (en) | 1998-11-19 | 2000-10-24 | Taiwan Semiconductor Manufacturing Company | Process technology architecture of embedded DRAM |
US6177340B1 (en) | 1999-02-18 | 2001-01-23 | Taiwan Semiconductor Manufacturing Company | Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure |
JP2000349172A (ja) * | 1999-02-26 | 2000-12-15 | Sony Corp | 半導体メモリセル |
JP3506633B2 (ja) * | 1999-04-09 | 2004-03-15 | 沖電気工業株式会社 | 半導体装置 |
US6219270B1 (en) * | 1999-05-24 | 2001-04-17 | U.S. Philips Corporation | Integrated circuit having dynamic memory with boosted plateline |
US6841821B2 (en) * | 1999-10-07 | 2005-01-11 | Monolithic System Technology, Inc. | Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same |
US6457108B1 (en) | 1999-10-07 | 2002-09-24 | Monolithic System Technology, Inc. | Method of operating a system-on-a-chip including entering a standby state in a non-volatile memory while operating the system-on-a-chip from a volatile memory |
US6329240B1 (en) | 1999-10-07 | 2001-12-11 | Monolithic System Technology, Inc. | Non-volatile memory cell and methods of fabricating and operating same |
CA2299991A1 (en) * | 2000-03-03 | 2001-09-03 | Mosaid Technologies Incorporated | A memory cell for embedded memories |
US6359802B1 (en) * | 2000-03-28 | 2002-03-19 | Intel Corporation | One-transistor and one-capacitor DRAM cell for logic process technology |
JP2002083942A (ja) * | 2000-09-06 | 2002-03-22 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置 |
JP2002208275A (ja) * | 2001-01-11 | 2002-07-26 | Matsushita Electric Ind Co Ltd | 半導体集積回路およびその検査方法 |
US6901052B2 (en) | 2001-05-04 | 2005-05-31 | Slt Logic Llc | System and method for policing multiple data flows and multi-protocol data flows |
US6944168B2 (en) * | 2001-05-04 | 2005-09-13 | Slt Logic Llc | System and method for providing transformation of multi-protocol packets in a data stream |
US6904057B2 (en) * | 2001-05-04 | 2005-06-07 | Slt Logic Llc | Method and apparatus for providing multi-protocol, multi-stage, real-time frame classification |
US7042848B2 (en) * | 2001-05-04 | 2006-05-09 | Slt Logic Llc | System and method for hierarchical policing of flows and subflows of a data stream |
JP2003257178A (ja) * | 2002-03-06 | 2003-09-12 | Matsushita Electric Ind Co Ltd | 半導体メモリ装置 |
JP4323749B2 (ja) * | 2002-03-25 | 2009-09-02 | パナソニック株式会社 | ダイナミックランダムアクセスメモリ |
US20110026323A1 (en) | 2009-07-30 | 2011-02-03 | International Business Machines Corporation | Gated Diode Memory Cells |
US8445946B2 (en) * | 2003-12-11 | 2013-05-21 | International Business Machines Corporation | Gated diode memory cells |
US7341765B2 (en) * | 2004-01-27 | 2008-03-11 | Battelle Energy Alliance, Llc | Metallic coatings on silicon substrates, and methods of forming metallic coatings on silicon substrates |
US7323379B2 (en) * | 2005-02-03 | 2008-01-29 | Mosys, Inc. | Fabrication process for increased capacitance in an embedded DRAM memory |
US20070170489A1 (en) * | 2006-01-26 | 2007-07-26 | Fang Gang-Feng | Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process |
US7382658B2 (en) * | 2006-01-26 | 2008-06-03 | Mosys, Inc. | Non-volatile memory embedded in a conventional logic process and methods for operating same |
JP5352077B2 (ja) | 2007-11-12 | 2013-11-27 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
TWI359422B (en) * | 2008-04-15 | 2012-03-01 | Faraday Tech Corp | 2t sram and associated cell structure |
US7929359B2 (en) * | 2008-11-13 | 2011-04-19 | Mosys, Inc. | Embedded DRAM with bias-independent capacitance |
US9911470B2 (en) | 2011-12-15 | 2018-03-06 | Nvidia Corporation | Fast-bypass memory circuit |
US8929128B2 (en) * | 2012-05-17 | 2015-01-06 | Semiconductor Energy Laboratory Co., Ltd. | Storage device and writing method of the same |
CN103632712A (zh) | 2012-08-27 | 2014-03-12 | 辉达公司 | 存储单元和存储器 |
US9685207B2 (en) | 2012-12-04 | 2017-06-20 | Nvidia Corporation | Sequential access memory with master-slave latch pairs and method of operating |
US10141930B2 (en) | 2013-06-04 | 2018-11-27 | Nvidia Corporation | Three state latch |
US9361972B1 (en) * | 2015-03-20 | 2016-06-07 | Intel Corporation | Charge level maintenance in a memory |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BE789501A (fr) * | 1971-09-30 | 1973-03-29 | Siemens Ag | Condensateur electrique dans un circuit integre, utilise notamment comme memoire pour une memoire a semiconducteur |
DE2441385C3 (de) * | 1974-08-29 | 1981-05-07 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum Vergrößern des Lesesignals bei einem Ein- Transistor-Speicherelement |
JPS52102690A (en) * | 1976-02-25 | 1977-08-29 | Hitachi Ltd | Semiconductor capacitance device |
US4439692A (en) * | 1981-12-07 | 1984-03-27 | Signetics Corporation | Feedback-controlled substrate bias generator |
JPS59165449A (ja) * | 1983-03-10 | 1984-09-18 | Toshiba Corp | 半導体記憶装置 |
US4591738A (en) * | 1983-10-27 | 1986-05-27 | International Business Machines Corporation | Charge pumping circuit |
US5051959A (en) * | 1985-08-14 | 1991-09-24 | Fujitsu Limited | Complementary semiconductor memory device including cell access transistor and word line driving transistor having channels of different conductivity type |
US4954731A (en) * | 1989-04-26 | 1990-09-04 | International Business Machines Corporation | Wordline voltage boosting circuits for complementary MOSFET dynamic memories |
US5166554A (en) * | 1990-10-02 | 1992-11-24 | Reddy Chitranjan N | Boot-strapped decoder circuit |
US5075571A (en) * | 1991-01-02 | 1991-12-24 | International Business Machines Corp. | PMOS wordline boost cricuit for DRAM |
KR950009815B1 (ko) * | 1991-12-23 | 1995-08-28 | 삼성전자주식회사 | 트리플웰 구조를 가지는 고집적 반도체 메모리 장치 |
KR100258337B1 (ko) * | 1992-10-31 | 2000-06-01 | 윤종용 | 반도체 메모리 장치 |
JP2709783B2 (ja) * | 1992-12-17 | 1998-02-04 | 三菱電機株式会社 | 昇圧回路 |
JP2921812B2 (ja) * | 1992-12-24 | 1999-07-19 | シャープ株式会社 | 不揮発性半導体記憶装置 |
-
1994
- 1994-12-14 US US08/355,956 patent/US5600598A/en not_active Expired - Lifetime
-
1995
- 1995-12-08 EP EP03002891A patent/EP1336970B1/de not_active Expired - Lifetime
- 1995-12-08 EP EP95119362A patent/EP0717413B1/de not_active Expired - Lifetime
- 1995-12-08 DE DE69531090T patent/DE69531090T2/de not_active Expired - Lifetime
- 1995-12-08 DE DE69536143T patent/DE69536143D1/de not_active Expired - Lifetime
- 1995-12-13 JP JP32439195A patent/JP3182067B2/ja not_active Expired - Fee Related
-
1997
- 1997-01-23 US US08/786,922 patent/US5694355A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH08264730A (ja) | 1996-10-11 |
JP3182067B2 (ja) | 2001-07-03 |
EP1336970B1 (de) | 2011-02-23 |
DE69531090T2 (de) | 2004-05-13 |
EP0717413B1 (de) | 2003-06-18 |
DE69531090D1 (de) | 2003-07-24 |
EP0717413A3 (de) | 1999-01-07 |
EP1336970A3 (de) | 2005-01-05 |
EP0717413A2 (de) | 1996-06-19 |
US5694355A (en) | 1997-12-02 |
EP1336970A2 (de) | 2003-08-20 |
US5600598A (en) | 1997-02-04 |
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