DE69529775D1 - Verfahren zur Herstellung einer Damaszenstruktur mit einer WGe Polierstoppschicht - Google Patents

Verfahren zur Herstellung einer Damaszenstruktur mit einer WGe Polierstoppschicht

Info

Publication number
DE69529775D1
DE69529775D1 DE69529775T DE69529775T DE69529775D1 DE 69529775 D1 DE69529775 D1 DE 69529775D1 DE 69529775 T DE69529775 T DE 69529775T DE 69529775 T DE69529775 T DE 69529775T DE 69529775 D1 DE69529775 D1 DE 69529775D1
Authority
DE
Germany
Prior art keywords
wge
producing
stop layer
polishing stop
damascus structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69529775T
Other languages
English (en)
Other versions
DE69529775T2 (de
Inventor
Rajiv Vasant Joshi
Manu Jamnadas Tejwani
Kris Venkatraman Srikrishnan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69529775D1 publication Critical patent/DE69529775D1/de
Application granted granted Critical
Publication of DE69529775T2 publication Critical patent/DE69529775T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53219—Aluminium alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H01L23/53247—Noble-metal alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12486—Laterally noncoextensive components [e.g., embedded, etc.]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12528—Semiconductor component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12674—Ge- or Si-base component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12736—Al-base component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12771—Transition metal-base component
    • Y10T428/12806—Refractory [Group IVB, VB, or VIB] metal-base component
    • Y10T428/12826—Group VIB metal-base component
    • Y10T428/1284—W-base component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12771—Transition metal-base component
    • Y10T428/12861—Group VIII or IB metal-base component
    • Y10T428/12889—Au-base component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12771—Transition metal-base component
    • Y10T428/12861—Group VIII or IB metal-base component
    • Y10T428/12896—Ag-base component

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
DE69529775T 1994-08-05 1995-07-05 Verfahren zur Herstellung einer Damaszenstruktur mit einer WGe Polierstoppschicht Expired - Lifetime DE69529775T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US28660594A 1994-08-05 1994-08-05

Publications (2)

Publication Number Publication Date
DE69529775D1 true DE69529775D1 (de) 2003-04-03
DE69529775T2 DE69529775T2 (de) 2003-10-16

Family

ID=23099349

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69513459T Expired - Lifetime DE69513459T2 (de) 1994-08-05 1995-07-05 Verfahren zur Herstellung einer Al-Ge Legierung mit einer WGe Polierstoppschicht
DE69529775T Expired - Lifetime DE69529775T2 (de) 1994-08-05 1995-07-05 Verfahren zur Herstellung einer Damaszenstruktur mit einer WGe Polierstoppschicht

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69513459T Expired - Lifetime DE69513459T2 (de) 1994-08-05 1995-07-05 Verfahren zur Herstellung einer Al-Ge Legierung mit einer WGe Polierstoppschicht

Country Status (6)

Country Link
US (4) US5856026A (de)
EP (2) EP0697730B1 (de)
JP (1) JP3083735B2 (de)
KR (1) KR0177537B1 (de)
DE (2) DE69513459T2 (de)
TW (1) TW344101B (de)

Families Citing this family (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE188863T1 (de) * 1994-02-25 2000-02-15 Fischell Robert Stent
EP0697730B1 (de) * 1994-08-05 1999-11-24 International Business Machines Corporation Verfahren zur Herstellung einer Al-Ge Legierung mit einer WGe Polierstoppschicht
US5789317A (en) * 1996-04-12 1998-08-04 Micron Technology, Inc. Low temperature reflow method for filling high aspect ratio contacts
US6429120B1 (en) 2000-01-18 2002-08-06 Micron Technology, Inc. Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals
US6309971B1 (en) 1996-08-01 2001-10-30 Cypress Semiconductor Corporation Hot metallization process
US5916453A (en) * 1996-09-20 1999-06-29 Fujitsu Limited Methods of planarizing structures on wafers and substrates by polishing
JP3583562B2 (ja) 1996-10-18 2004-11-04 株式会社東芝 半導体装置
KR100221656B1 (ko) * 1996-10-23 1999-09-15 구본준 배선 형성 방법
US6171957B1 (en) * 1997-07-16 2001-01-09 Mitsubishi Denki Kabushiki Kaisha Manufacturing method of semiconductor device having high pressure reflow process
US6100184A (en) * 1997-08-20 2000-08-08 Sematech, Inc. Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer
US6140228A (en) 1997-11-13 2000-10-31 Cypress Semiconductor Corporation Low temperature metallization process
US6211073B1 (en) 1998-02-27 2001-04-03 Micron Technology, Inc. Methods for making copper and other metal interconnections in integrated circuits
US6015749A (en) * 1998-05-04 2000-01-18 Taiwan Semiconductor Manufacturing Company Method to improve adhesion between copper and titanium nitride, for copper interconnect structures, via the use of an ion implantation procedure
US6362097B1 (en) * 1998-07-14 2002-03-26 Applied Komatsu Technlology, Inc. Collimated sputtering of semiconductor and other films
KR100265772B1 (ko) * 1998-07-22 2000-10-02 윤종용 반도체 장치의 배선구조 및 그 제조방법
US6287977B1 (en) 1998-07-31 2001-09-11 Applied Materials, Inc. Method and apparatus for forming improved metal interconnects
US6284656B1 (en) 1998-08-04 2001-09-04 Micron Technology, Inc. Copper metallurgy in integrated circuits
US6288442B1 (en) * 1998-09-10 2001-09-11 Micron Technology, Inc. Integrated circuit with oxidation-resistant polymeric layer
US6004188A (en) * 1998-09-10 1999-12-21 Chartered Semiconductor Manufacturing Ltd. Method for forming copper damascene structures by using a dual CMP barrier layer
US6051496A (en) * 1998-09-17 2000-04-18 Taiwan Semiconductor Manufacturing Company Use of stop layer for chemical mechanical polishing of CU damascene
US6180480B1 (en) 1998-09-28 2001-01-30 International Business Machines Corporation Germanium or silicon-germanium deep trench fill by melt-flow process
US6069082A (en) * 1998-10-13 2000-05-30 Chartered Semiconductor Manufacturing Ltd. Method to prevent dishing in damascene CMP process
US6274253B1 (en) * 1998-11-13 2001-08-14 Micron Technology, Inc. Processing methods for providing metal-comprising materials within high aspect ratio openings
US6143657A (en) * 1999-01-04 2000-11-07 Taiwan Semiconductor Manufacturing Company Method of increasing the stability of a copper to copper interconnection process and structure manufactured thereby
US6130162A (en) * 1999-01-04 2000-10-10 Taiwan Semiconductor Manufacturing Company Method of preparing passivated copper line and device manufactured thereby
US6174799B1 (en) * 1999-01-05 2001-01-16 Advanced Micro Devices, Inc. Graded compound seed layers for semiconductors
US6114246A (en) * 1999-01-07 2000-09-05 Vlsi Technology, Inc. Method of using a polish stop film to control dishing during copper chemical mechanical polishing
US20020127845A1 (en) * 1999-03-01 2002-09-12 Paul A. Farrar Conductive structures in integrated circuits
US6281127B1 (en) 1999-04-15 2001-08-28 Taiwan Semiconductor Manufacturing Company Self-passivation procedure for a copper damascene structure
US6194307B1 (en) 1999-04-26 2001-02-27 Taiwan Semiconductor Manufacturing Company Elimination of copper line damages for damascene process
US6071808A (en) * 1999-06-23 2000-06-06 Lucent Technologies Inc. Method of passivating copper interconnects in a semiconductor
US6046108A (en) 1999-06-25 2000-04-04 Taiwan Semiconductor Manufacturing Company Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby
US6387810B2 (en) * 1999-06-28 2002-05-14 International Business Machines Corporation Method for homogenizing device parameters through photoresist planarization
US6248665B1 (en) 1999-07-06 2001-06-19 Taiwan Semiconductor Manufacturing Company Delamination improvement between Cu and dielectrics for damascene process
US6391780B1 (en) 1999-08-23 2002-05-21 Taiwan Semiconductor Manufacturing Company Method to prevent copper CMP dishing
US6248002B1 (en) 1999-10-20 2001-06-19 Taiwan Semiconductor Manufacturing Company Obtaining the better defect performance of the fuse CMP process by adding slurry polish on more soft pad after slurry polish
US6114243A (en) * 1999-11-15 2000-09-05 Chartered Semiconductor Manufacturing Ltd Method to avoid copper contamination on the sidewall of a via or a dual damascene structure
US6344419B1 (en) 1999-12-03 2002-02-05 Applied Materials, Inc. Pulsed-mode RF bias for sidewall coverage improvement
US6627541B1 (en) * 1999-12-15 2003-09-30 Texas Instruments Incorporated Reflow method for construction of conductive vias
US6361880B1 (en) 1999-12-22 2002-03-26 International Business Machines Corporation CVD/PVD/CVD/PVD fill process
US6455427B1 (en) 1999-12-30 2002-09-24 Cypress Semiconductor Corp. Method for forming void-free metallization in an integrated circuit
US6969448B1 (en) 1999-12-30 2005-11-29 Cypress Semiconductor Corp. Method for forming a metallization structure in an integrated circuit
US7211512B1 (en) * 2000-01-18 2007-05-01 Micron Technology, Inc. Selective electroless-plated copper metallization
US7262130B1 (en) 2000-01-18 2007-08-28 Micron Technology, Inc. Methods for making integrated-circuit wiring from copper, silver, gold, and other metals
US6376370B1 (en) * 2000-01-18 2002-04-23 Micron Technology, Inc. Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy
US6420262B1 (en) 2000-01-18 2002-07-16 Micron Technology, Inc. Structures and methods to enhance copper metallization
US6339029B1 (en) 2000-01-19 2002-01-15 Taiwan Semiconductor Manufacturing Company Method to form copper interconnects
US6329290B1 (en) * 2000-02-24 2001-12-11 Conexant Systems, Inc. Method for fabrication and structure for high aspect ratio vias
US6423629B1 (en) * 2000-05-31 2002-07-23 Kie Y. Ahn Multilevel copper interconnects with low-k dielectrics and air gaps
US6335261B1 (en) 2000-05-31 2002-01-01 International Business Machines Corporation Directional CVD process with optimized etchback
US6674167B1 (en) * 2000-05-31 2004-01-06 Micron Technology, Inc. Multilevel copper interconnect with double passivation
US6554979B2 (en) 2000-06-05 2003-04-29 Applied Materials, Inc. Method and apparatus for bias deposition in a modulating electric field
DE10032792A1 (de) * 2000-06-28 2002-01-17 Infineon Technologies Ag Verfahren zur Herstellung einer Verdrahtung für Kontaktlöcher
US6429118B1 (en) 2000-09-18 2002-08-06 Taiwan Semiconductor Manufacturing Company Elimination of electrochemical deposition copper line damage for damascene processing
US6383935B1 (en) 2000-10-16 2002-05-07 Taiwan Semiconductor Manufacturing Company Method of reducing dishing and erosion using a sacrificial layer
US6433402B1 (en) * 2000-11-16 2002-08-13 Advanced Micro Devices, Inc. Selective copper alloy deposition
US7067440B1 (en) 2001-08-24 2006-06-27 Novellus Systems, Inc. Gap fill for high aspect ratio structures
US6746591B2 (en) 2001-10-16 2004-06-08 Applied Materials Inc. ECP gap fill by modulating the voltate on the seed layer to increase copper concentration inside feature
US6794290B1 (en) 2001-12-03 2004-09-21 Novellus Systems, Inc. Method of chemical modification of structure topography
US7138719B2 (en) * 2002-08-29 2006-11-21 Micron Technology, Inc. Trench interconnect structure and formation method
US7122485B1 (en) 2002-12-09 2006-10-17 Novellus Systems, Inc. Deposition profile modification through process chemistry
US7220665B2 (en) * 2003-08-05 2007-05-22 Micron Technology, Inc. H2 plasma treatment
US7078312B1 (en) 2003-09-02 2006-07-18 Novellus Systems, Inc. Method for controlling etch process repeatability
US7476621B1 (en) 2003-12-10 2009-01-13 Novellus Systems, Inc. Halogen-free noble gas assisted H2 plasma etch process in deposition-etch-deposition gap fill
US7344996B1 (en) 2005-06-22 2008-03-18 Novellus Systems, Inc. Helium-based etch process in deposition-etch-deposition gap fill
US7163896B1 (en) 2003-12-10 2007-01-16 Novellus Systems, Inc. Biased H2 etch process in deposition-etch-deposition gap fill
US7199045B2 (en) * 2004-05-26 2007-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-filled openings for submicron devices and methods of manufacture thereof
US7217658B1 (en) 2004-09-07 2007-05-15 Novellus Systems, Inc. Process modulation to prevent structure erosion during gap fill
US7176039B1 (en) 2004-09-21 2007-02-13 Novellus Systems, Inc. Dynamic modification of gap fill process characteristics
US7381451B1 (en) 2004-11-17 2008-06-03 Novellus Systems, Inc. Strain engineering—HDP thin film with tensile stress for FEOL and other applications
US7211525B1 (en) 2005-03-16 2007-05-01 Novellus Systems, Inc. Hydrogen treatment enhanced gap fill
US20070052107A1 (en) * 2005-09-05 2007-03-08 Cheng-Ming Weng Multi-layered structure and fabricating method thereof and dual damascene structure, interconnect structure and capacitor
US7563714B2 (en) * 2006-01-13 2009-07-21 International Business Machines Corporation Low resistance and inductance backside through vias and methods of fabricating same
US7491643B2 (en) * 2006-05-24 2009-02-17 International Business Machines Corporation Method and structure for reducing contact resistance between silicide contact and overlying metallization
US7482245B1 (en) 2006-06-20 2009-01-27 Novellus Systems, Inc. Stress profile modulation in STI gap fill
US7648921B2 (en) * 2006-09-22 2010-01-19 Macronix International Co., Ltd. Method of forming dielectric layer
US7666781B2 (en) * 2006-11-22 2010-02-23 International Business Machines Corporation Interconnect structures with improved electromigration resistance and methods for forming such interconnect structures
US7629212B2 (en) * 2007-03-19 2009-12-08 Texas Instruments Incorporated Doped WGe to form dual metal gates
US7651939B2 (en) 2007-05-01 2010-01-26 Freescale Semiconductor, Inc Method of blocking a void during contact formation
US7994034B2 (en) * 2008-03-10 2011-08-09 Ovonyx, Inc. Temperature and pressure control methods to fill features with programmable resistance and switching devices
KR100905872B1 (ko) * 2007-08-24 2009-07-03 주식회사 하이닉스반도체 반도체 소자의 금속배선 형성 방법
US8133797B2 (en) * 2008-05-16 2012-03-13 Novellus Systems, Inc. Protective layer to enable damage free gap fill
KR20120124634A (ko) * 2011-05-04 2012-11-14 삼성전자주식회사 반도체 장치의 제조 방법 및 이를 포함하는 반도체 패키지의 제조 방법
US8697562B2 (en) 2011-06-23 2014-04-15 Richard L. McCreery Metal contacts for molecular device junctions and surface-diffusion-mediated deposition
US8575000B2 (en) * 2011-07-19 2013-11-05 SanDisk Technologies, Inc. Copper interconnects separated by air gaps and method of making thereof
US8652951B2 (en) * 2012-02-13 2014-02-18 Applied Materials, Inc. Selective epitaxial germanium growth on silicon-trench fill and in situ doping
US9997458B2 (en) 2012-05-14 2018-06-12 Imec Vzw Method for manufacturing germamde interconnect structures and corresponding interconnect structures
CN106463358B (zh) * 2014-06-16 2020-04-24 英特尔公司 金属互连件的接缝愈合
US9953940B2 (en) 2015-06-26 2018-04-24 International Business Machines Corporation Corrosion resistant aluminum bond pad structure
KR102383369B1 (ko) * 2016-06-17 2022-04-05 고쿠리츠켄큐카이하츠호진 상교기쥬츠 소고켄큐쇼 텅스텐과 게르마늄의 화합물막 및 반도체 장치
US11183443B2 (en) * 2019-06-13 2021-11-23 Nanya Technology Corporation Semiconductor structure and method for manufacturing the same

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL278654A (de) * 1961-06-08
US3222630A (en) * 1961-06-26 1965-12-07 Texas Instruments Inc Aluminum-germanium contact
US3501829A (en) * 1966-07-18 1970-03-24 United Aircraft Corp Method of applying contacts to a microcircuit
US4022625A (en) * 1974-12-24 1977-05-10 Nl Industries, Inc. Polishing composition and method of polishing
US4188710A (en) * 1978-08-11 1980-02-19 The United States Of America As Represented By The Secretary Of The Navy Ohmic contacts for group III-V n-type semiconductors using epitaxial germanium films
US4207546A (en) * 1978-12-07 1980-06-10 United Technologies Corporation Phase and amplitude programmable internal mixing SAW signal processor
US4301188A (en) * 1979-10-01 1981-11-17 Bell Telephone Laboratories, Incorporated Process for producing contact to GaAs active region
US4321099A (en) * 1979-11-13 1982-03-23 Nasa Method of fabricating Schottky barrier solar cell
JPH01107558A (ja) * 1987-10-20 1989-04-25 Matsushita Electric Ind Co Ltd 金属薄膜配線の製造方法
US5121174A (en) * 1987-10-23 1992-06-09 Vitesse Semiconductor Corporation Gate-to-ohmic metal contact scheme for III-V devices
DE68927116T2 (de) * 1988-01-19 1997-02-06 Fujimi Inc Poliermasse
US4908182A (en) * 1988-04-11 1990-03-13 Polytechnic University Rapidly solidified high strength, ductile dispersion-hardened tungsten-rich alloys
JPH02257640A (ja) * 1989-03-30 1990-10-18 Oki Electric Ind Co Ltd 半導体素子の製造方法
JPH03122273A (ja) * 1989-10-06 1991-05-24 Hitachi Ltd マイクロ波を用いた成膜装置
KR960001601B1 (ko) * 1992-01-23 1996-02-02 삼성전자주식회사 반도체 장치의 접촉구 매몰방법 및 구조
JP2841976B2 (ja) * 1990-11-28 1998-12-24 日本電気株式会社 半導体装置およびその製造方法
US5143867A (en) * 1991-02-13 1992-09-01 International Business Machines Corporation Method for depositing interconnection metallurgy using low temperature alloy processes
JPH04334019A (ja) * 1991-05-09 1992-11-20 Hitachi Ltd 化合物半導体装置の製造方法
US5171412A (en) * 1991-08-23 1992-12-15 Applied Materials, Inc. Material deposition method for integrated circuit manufacturing
US5262354A (en) * 1992-02-26 1993-11-16 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
JP2547935B2 (ja) * 1992-04-30 1996-10-30 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体集積回路の相互接続構造の形成方法
US5314840A (en) * 1992-12-18 1994-05-24 International Business Machines Corporation Method for forming an antifuse element with electrical or optical programming
US5356513A (en) * 1993-04-22 1994-10-18 International Business Machines Corporation Polishstop planarization method and structure
US5300130A (en) * 1993-07-26 1994-04-05 Saint Gobain/Norton Industrial Ceramics Corp. Polishing material
US5332467A (en) * 1993-09-20 1994-07-26 Industrial Technology Research Institute Chemical/mechanical polishing for ULSI planarization
EP0697730B1 (de) * 1994-08-05 1999-11-24 International Business Machines Corporation Verfahren zur Herstellung einer Al-Ge Legierung mit einer WGe Polierstoppschicht
US5527423A (en) * 1994-10-06 1996-06-18 Cabot Corporation Chemical mechanical polishing slurry for metal layers

Also Published As

Publication number Publication date
TW344101B (en) 1998-11-01
US5897370A (en) 1999-04-27
EP0697730B1 (de) 1999-11-24
JP3083735B2 (ja) 2000-09-04
JPH0864599A (ja) 1996-03-08
US5856026A (en) 1999-01-05
DE69513459T2 (de) 2000-10-26
US5731245A (en) 1998-03-24
EP0697730A3 (de) 1996-08-14
DE69529775T2 (de) 2003-10-16
KR960009109A (ko) 1996-03-22
EP0915501A1 (de) 1999-05-12
US5877084A (en) 1999-03-02
EP0915501B1 (de) 2003-02-26
DE69513459D1 (de) 1999-12-30
KR0177537B1 (ko) 1999-04-15
EP0697730A2 (de) 1996-02-21

Similar Documents

Publication Publication Date Title
DE69529775D1 (de) Verfahren zur Herstellung einer Damaszenstruktur mit einer WGe Polierstoppschicht
DE59409157D1 (de) Verfahren zur Herstellung einer Schicht mit reduzierten mechanischen Spannungen
DE69727655D1 (de) Verfahren zur herstellung einer cdte-schicht
DE69703130D1 (de) Verfahren zur Herstellung einer Gradientenschicht mit einer keramischen Deckschicht
DE69520837D1 (de) Verfahren zur herstellung einer mehrschichtigen saugfähigen struktur
DE69123228D1 (de) Verfahren zur Herstellung einer chemisch adsorbierten Schicht
DE69621723D1 (de) Verfahren zur Herstellung einer Schicht
ATE179239T1 (de) Verfahren zur herstellung einer verrohrung im bohrloch
DE68905556D1 (de) Verfahren zur herstellung einer transparenten schicht.
DE69705334D1 (de) Lumineszenzelement mit einer lichtdurchlässigen Reflexionsschicht und Verfahren zur Herstellung desselben
DE69621385D1 (de) Verfahren zur herstellung einer halbleiteranordnung mit kristalldefekten
DE69126949D1 (de) Verfahren zur Herstellung einer einkristallinen Schicht
DE69504896D1 (de) Synthetische Diamantschicht mit verringerter Biegung und Verfahren zu ihrer Herstellung
DE69710242D1 (de) Verfahren zur Herstellung eines mit Diamant beschichteten Verbundkörpers
DE69410137D1 (de) Verfahren zur Herstellung einer chalkopyrit-Halbleiterschicht
DE59408258D1 (de) Verfahren zur herstellung einer hartstoffschicht
DE69526661D1 (de) Verfahren zur herstellung einer verbundglasplatte
DE69520538D1 (de) Verfahren zur Herstellung einer dünnen polykristallinen Halbleiterschicht
DE69509594D1 (de) Verfahren zur Herstellung einer Diamantschicht
DE69506331D1 (de) Verfahren zur Herstellung einer synthetischen Diamantschicht mit reduzierter Beugung
DE69604789D1 (de) Verfahren zur herstellung einer gebogenen verbundglasscheibe
DE69323585D1 (de) Verfahren zur herstellung einer teppichfliese
DE69002502D1 (de) Verfahren zur herstellung einer metalloxidschicht.
ATA66796A (de) Verfahren zur herstellung einer präparation enthaltend einen hochgereinigten komplex
DE68902597D1 (de) Verfahren zur herstellung einer zirkoniumoxidschicht.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Representative=s name: DUSCHER, R., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 7