DE69332728D1 - Datenausgangspuffer in Halbleiterspeicheranordnungen - Google Patents

Datenausgangspuffer in Halbleiterspeicheranordnungen

Info

Publication number
DE69332728D1
DE69332728D1 DE69332728T DE69332728T DE69332728D1 DE 69332728 D1 DE69332728 D1 DE 69332728D1 DE 69332728 T DE69332728 T DE 69332728T DE 69332728 T DE69332728 T DE 69332728T DE 69332728 D1 DE69332728 D1 DE 69332728D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
data output
memory devices
output buffers
buffers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69332728T
Other languages
English (en)
Other versions
DE69332728T2 (de
Inventor
Ho-Cheol Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE69332728D1 publication Critical patent/DE69332728D1/de
Application granted granted Critical
Publication of DE69332728T2 publication Critical patent/DE69332728T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
DE69332728T 1992-10-02 1993-10-01 Datenausgangspuffer in Halbleiterspeicheranordnungen Expired - Lifetime DE69332728T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92018133A KR950010564B1 (en) 1992-10-02 1992-10-02 Data output buffer of synchronous semiconductor memory device

Publications (2)

Publication Number Publication Date
DE69332728D1 true DE69332728D1 (de) 2003-04-03
DE69332728T2 DE69332728T2 (de) 2003-12-18

Family

ID=19340550

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69332728T Expired - Lifetime DE69332728T2 (de) 1992-10-02 1993-10-01 Datenausgangspuffer in Halbleiterspeicheranordnungen
DE69329410T Expired - Lifetime DE69329410T2 (de) 1992-10-02 1993-10-01 Datenausgangspuffer in Halbleiterspeicheranordnungen

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE69329410T Expired - Lifetime DE69329410T2 (de) 1992-10-02 1993-10-01 Datenausgangspuffer in Halbleiterspeicheranordnungen

Country Status (7)

Country Link
US (1) US5384750A (de)
EP (2) EP0591008B1 (de)
JP (1) JP3717949B2 (de)
KR (1) KR950010564B1 (de)
CN (1) CN1054940C (de)
DE (2) DE69332728T2 (de)
TW (1) TW229308B (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2616567B2 (ja) * 1994-09-28 1997-06-04 日本電気株式会社 半導体記憶装置
JP2697633B2 (ja) * 1994-09-30 1998-01-14 日本電気株式会社 同期型半導体記憶装置
US5623638A (en) * 1994-11-22 1997-04-22 Advanced Micro Devices, Inc. Memory control unit with programmable edge generator to minimize delay periods for critical DRAM timing parameters
US5526320A (en) 1994-12-23 1996-06-11 Micron Technology Inc. Burst EDO memory device
US5717654A (en) * 1995-02-10 1998-02-10 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing
JPH09139080A (ja) * 1995-06-01 1997-05-27 Texas Instr Inc <Ti> ダイナミックランダムアクセスメモリに使用する出力バッファユニットおよび信号処理方法
US5873114A (en) * 1995-08-18 1999-02-16 Advanced Micro Devices, Inc. Integrated processor and memory control unit including refresh queue logic for refreshing DRAM during idle cycles
KR0167683B1 (ko) * 1995-09-11 1999-02-01 김광호 동기메모리의 고주파 동작용 데이타 출력버퍼 제어방법
US5692165A (en) * 1995-09-12 1997-11-25 Micron Electronics Inc. Memory controller with low skew control signal
KR0164807B1 (ko) * 1995-12-22 1999-02-01 김광호 반도체 메모리 장치의 데이타 출력버퍼 제어회로
US5666324A (en) * 1996-03-15 1997-09-09 Mitsubishi Denki Kabushiki Kaisha Clock synchronous semiconductor memory device having current consumption reduced
JP3703241B2 (ja) * 1997-01-28 2005-10-05 Ｎｅｃエレクトロニクス株式会社 半導体メモリ装置
US6243797B1 (en) 1997-02-18 2001-06-05 Micron Technlogy, Inc. Multiplexed semiconductor data transfer arrangement with timing signal generator
KR100486199B1 (ko) * 1997-08-11 2005-09-12 삼성전자주식회사 반도체메모리장치의하이임피던스제어신호발생회로
KR100252048B1 (ko) * 1997-11-18 2000-05-01 윤종용 반도체 메모리장치의 데이터 마스킹 회로 및 데이터 마스킹방법
KR100318263B1 (ko) 1999-06-28 2001-12-24 박종섭 패킷명령어 구동형 메모리소자
JP2001052498A (ja) * 1999-08-05 2001-02-23 Toshiba Corp 半導体記憶装置
KR100311044B1 (ko) * 1999-10-05 2001-10-18 윤종용 클럭 주파수에 따라 레이턴시 조절이 가능한 레이턴시 결정 회로 및 레이턴시 결정 방법
KR100468776B1 (ko) * 2002-12-10 2005-01-29 삼성전자주식회사 클락 지터의 영향을 감소시킬 수 있는 동기식 반도체메모리장치
KR100548563B1 (ko) * 2003-06-30 2006-02-02 주식회사 하이닉스반도체 Ｄｄｒ ｓｄｒａｍ 에서의 라이트 링잉 현상을 마스크하기위한 데이타 패스 제어 장치 및 방법
KR100557636B1 (ko) * 2003-12-23 2006-03-10 주식회사 하이닉스반도체 클럭신호를 이용한 데이터 스트로브 회로
US7054222B2 (en) * 2004-07-19 2006-05-30 Micron Technology, Inc. Write address synchronization useful for a DDR prefetch SDRAM
KR100654125B1 (ko) 2005-09-29 2006-12-08 주식회사 하이닉스반도체 반도체메모리소자의 데이터 출력장치
KR101143487B1 (ko) 2010-10-29 2012-05-15 에스케이하이닉스 주식회사 반도체 메모리 장치의

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4719601A (en) * 1986-05-02 1988-01-12 International Business Machine Corporation Column redundancy for two port random access memory
JPS63155340A (ja) * 1986-12-19 1988-06-28 Fujitsu Ltd 記憶装置の読出し方式
JP2740063B2 (ja) * 1990-10-15 1998-04-15 株式会社東芝 半導体記憶装置
TW198135B (de) * 1990-11-20 1993-01-11 Oki Electric Ind Co Ltd
JP3100622B2 (ja) * 1990-11-20 2000-10-16 沖電気工業株式会社 同期型ダイナミックｒａｍ

Also Published As

Publication number Publication date
EP0591008B1 (de) 2000-09-13
EP1026692A3 (de) 2000-12-20
CN1054940C (zh) 2000-07-26
DE69329410D1 (de) 2000-10-19
JP3717949B2 (ja) 2005-11-16
EP1026692A2 (de) 2000-08-09
US5384750A (en) 1995-01-24
EP1026692B1 (de) 2003-02-26
KR950010564B1 (en) 1995-09-19
DE69329410T2 (de) 2001-06-07
CN1089748A (zh) 1994-07-20
EP0591008A2 (de) 1994-04-06
EP0591008A3 (de) 1994-12-28
KR940010083A (ko) 1994-05-24
TW229308B (de) 1994-09-01
DE69332728T2 (de) 2003-12-18
JPH06203563A (ja) 1994-07-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition