DE69325838T2 - Halbleiter-FIFO-Speicher - Google Patents

Halbleiter-FIFO-Speicher

Info

Publication number
DE69325838T2
DE69325838T2 DE69325838T DE69325838T DE69325838T2 DE 69325838 T2 DE69325838 T2 DE 69325838T2 DE 69325838 T DE69325838 T DE 69325838T DE 69325838 T DE69325838 T DE 69325838T DE 69325838 T2 DE69325838 T2 DE 69325838T2
Authority
DE
Germany
Prior art keywords
semiconductor
fifo memory
fifo
memory
semiconductor fifo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69325838T
Other languages
English (en)
Other versions
DE69325838D1 (de
Inventor
Shotaro Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69325838D1 publication Critical patent/DE69325838D1/de
Publication of DE69325838T2 publication Critical patent/DE69325838T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/003—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation in serial memories
DE69325838T 1992-03-26 1993-03-25 Halbleiter-FIFO-Speicher Expired - Lifetime DE69325838T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4067853A JPH05274860A (ja) 1992-03-26 1992-03-26 半導体メモリ

Publications (2)

Publication Number Publication Date
DE69325838D1 DE69325838D1 (de) 1999-09-09
DE69325838T2 true DE69325838T2 (de) 2000-02-24

Family

ID=13356932

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69325838T Expired - Lifetime DE69325838T2 (de) 1992-03-26 1993-03-25 Halbleiter-FIFO-Speicher

Country Status (4)

Country Link
US (1) US5371708A (de)
EP (1) EP0562604B1 (de)
JP (1) JPH05274860A (de)
DE (1) DE69325838T2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0722171B1 (de) * 1995-01-12 2001-09-26 Intergraph Corporation Registerspeicher mit Umleitungsmöglichkeit
KR100197554B1 (ko) * 1995-09-30 1999-06-15 윤종용 반도체 메모리장치의 고속테스트 방법
US5592425A (en) * 1995-12-20 1997-01-07 Intel Corporation Method and apparatus for testing a memory where data is passed through the memory for comparison with data read from the memory
US6173425B1 (en) * 1998-04-15 2001-01-09 Integrated Device Technology, Inc. Methods of testing integrated circuits to include data traversal path identification information and related status information in test data streams
KR100276652B1 (ko) * 1998-05-18 2001-01-15 윤종용 반도체 메모리 장치 및 그 장치의 데이터 처리 방법
US5982700A (en) * 1998-05-21 1999-11-09 Integrated Device Technology, Inc. Buffer memory arrays having nonlinear columns for providing parallel data access capability and methods of operating same
US5978307A (en) * 1998-05-21 1999-11-02 Integrated Device Technology, Inc. Integrated circuit memory devices having partitioned multi-port memory arrays therein for increasing data bandwidth and methods of operating same
US5999478A (en) * 1998-05-21 1999-12-07 Integrated Device Technology, Inc. Highly integrated tri-port memory buffers having fast fall-through capability and methods of operating same
US6216205B1 (en) 1998-05-21 2001-04-10 Integrated Device Technology, Inc. Methods of controlling memory buffers having tri-port cache arrays therein
US7143197B1 (en) * 1999-11-08 2006-11-28 Agere Systems Inc. Method and system for monitoring a telecommunications signal transmission link
US6501698B1 (en) * 2000-11-01 2002-12-31 Enhanced Memory Systems, Inc. Structure and method for hiding DRAM cycle time behind a burst access
US7082071B2 (en) * 2001-08-23 2006-07-25 Integrated Device Technology, Inc. Integrated DDR/SDR flow control managers that support multiple queues and MUX, DEMUX and broadcast operating modes
US6795360B2 (en) * 2001-08-23 2004-09-21 Integrated Device Technology, Inc. Fifo memory devices that support all four combinations of DDR or SDR write modes with DDR or SDR read modes
US7120075B1 (en) 2003-08-18 2006-10-10 Integrated Device Technology, Inc. Multi-FIFO integrated circuit devices that support multi-queue operating modes with enhanced write path and read path queue switching
US7042792B2 (en) * 2004-01-14 2006-05-09 Integrated Device Technology, Inc. Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays
US7425841B2 (en) 2004-02-14 2008-09-16 Tabula Inc. Configurable circuits, IC's, and systems
US7246300B1 (en) 2004-08-06 2007-07-17 Integrated Device Technology Inc. Sequential flow-control and FIFO memory devices having error detection and correction capability with diagnostic bit generation
US7330050B2 (en) 2004-11-08 2008-02-12 Tabula, Inc. Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements
US7268586B1 (en) 2004-11-08 2007-09-11 Tabula, Inc. Method and apparatus for accessing stored data in a reconfigurable IC
US7317331B2 (en) 2004-11-08 2008-01-08 Tabula, Inc. Reconfigurable IC that has sections running at different reconfiguration rates
US7230869B1 (en) * 2005-03-15 2007-06-12 Jason Redgrave Method and apparatus for accessing contents of memory cells
US7669097B1 (en) 2006-03-27 2010-02-23 Tabula, Inc. Configurable IC with error detection and correction circuitry
US7529992B1 (en) 2006-03-27 2009-05-05 Tabula, Inc. Configurable integrated circuit with error correcting circuitry
US8112468B1 (en) 2007-03-22 2012-02-07 Tabula, Inc. Method and apparatus for performing an operation with a plurality of sub-operations in a configurable IC
US8248101B2 (en) * 2007-09-06 2012-08-21 Tabula, Inc. Reading configuration data from internal storage node of configuration storage circuit
US8645617B2 (en) * 2008-12-09 2014-02-04 Rambus Inc. Memory device for concurrent and pipelined memory operations

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3789987T2 (de) * 1986-03-24 1994-12-15 Nippon Electric Co Halbleiterspeichervorrichtung mit einem Testmodus und einem Standardmodusbetrieb.
US4800530A (en) * 1986-08-19 1989-01-24 Kabushiki Kasiha Toshiba Semiconductor memory system with dynamic random access memory cells
US4802122A (en) * 1987-04-28 1989-01-31 Advanced Micro Devices, Inc. Fast flush for a first-in first-out memory
JP2793184B2 (ja) * 1987-07-27 1998-09-03 日本電気アイシーマイコンシステム株式会社 半導体記憶装置
JPH01158700A (ja) * 1987-12-15 1989-06-21 Sony Corp 半導体記憶装置
US5150327A (en) * 1988-10-31 1992-09-22 Matsushita Electric Industrial Co., Ltd. Semiconductor memory and video signal processing circuit having the same
EP0460692B1 (de) * 1990-06-08 1996-01-10 Kabushiki Kaisha Toshiba Halbleiterspeicher mit Fehlerbehandlungsschaltung

Also Published As

Publication number Publication date
US5371708A (en) 1994-12-06
EP0562604A2 (de) 1993-09-29
JPH05274860A (ja) 1993-10-22
EP0562604A3 (en) 1993-11-03
DE69325838D1 (de) 1999-09-09
EP0562604B1 (de) 1999-08-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKYO, JP