DE69327145T2 - Herstellungsverfahren für ein CMOS-Bauteil - Google Patents

Herstellungsverfahren für ein CMOS-Bauteil

Info

Publication number
DE69327145T2
DE69327145T2 DE69327145T DE69327145T DE69327145T2 DE 69327145 T2 DE69327145 T2 DE 69327145T2 DE 69327145 T DE69327145 T DE 69327145T DE 69327145 T DE69327145 T DE 69327145T DE 69327145 T2 DE69327145 T2 DE 69327145T2
Authority
DE
Germany
Prior art keywords
manufacturing process
cmos device
cmos
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69327145T
Other languages
English (en)
Other versions
DE69327145D1 (de
Inventor
Derryl Dwayne John Allman
Dim-Lee Kwong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
NCR International Inc
Original Assignee
Symbios Inc
NCR International Inc
Hyundai Electronics America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Symbios Inc, NCR International Inc, Hyundai Electronics America Inc filed Critical Symbios Inc
Application granted granted Critical
Publication of DE69327145D1 publication Critical patent/DE69327145D1/de
Publication of DE69327145T2 publication Critical patent/DE69327145T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/945—Special, e.g. metal

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69327145T 1992-10-23 1993-10-12 Herstellungsverfahren für ein CMOS-Bauteil Expired - Fee Related DE69327145T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/965,822 US5340770A (en) 1992-10-23 1992-10-23 Method of making a shallow junction by using first and second SOG layers

Publications (2)

Publication Number Publication Date
DE69327145D1 DE69327145D1 (de) 2000-01-05
DE69327145T2 true DE69327145T2 (de) 2000-06-29

Family

ID=25510543

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69327145T Expired - Fee Related DE69327145T2 (de) 1992-10-23 1993-10-12 Herstellungsverfahren für ein CMOS-Bauteil

Country Status (4)

Country Link
US (1) US5340770A (de)
EP (1) EP0594339B1 (de)
JP (1) JP3466244B2 (de)
DE (1) DE69327145T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3175973B2 (ja) * 1992-04-28 2001-06-11 株式会社東芝 半導体装置およびその製造方法
US5888890A (en) * 1994-08-12 1999-03-30 Lg Semicon Co., Ltd. Method of manufacturing field effect transistor
KR0146522B1 (ko) * 1995-03-22 1998-11-02 김주용 반도체 소자의 트랜지스터 제조방법
US5569624A (en) * 1995-06-05 1996-10-29 Regents Of The University Of California Method for shallow junction formation
US5994209A (en) * 1996-11-13 1999-11-30 Applied Materials, Inc. Methods and apparatus for forming ultra-shallow doped regions using doped silicon oxide films
US6025242A (en) * 1999-01-25 2000-02-15 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions including an insulating spacer by thermal oxidation creating taper-shaped isolation
US5998273A (en) * 1999-01-25 1999-12-07 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions
US5998248A (en) * 1999-01-25 1999-12-07 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions with tapered spacer in isolation region
US6022771A (en) * 1999-01-25 2000-02-08 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions and sidewall spacers creating taper-shaped isolation where the source and drain regions meet the gate regions
KR100397370B1 (ko) * 2001-10-29 2003-09-13 한국전자통신연구원 얕은 접합을 갖는 집적회로의 제조 방법
KR100425582B1 (ko) 2001-11-22 2004-04-06 한국전자통신연구원 얕은 소오스/드레인 접합 영역을 갖는 모스 트랜지스터의제조방법
JP4964780B2 (ja) * 2004-11-12 2012-07-04 スタッツ・チップパック・インコーポレイテッド ワイヤボンド相互接続、半導体パッケージ、および、ワイヤボンド相互接続の形成方法
US7868468B2 (en) * 2004-11-12 2011-01-11 Stats Chippac Ltd. Wire bonding structure and method that eliminates special wire bondable finish and reduces bonding pitch on substrates
US8519517B2 (en) 2004-11-13 2013-08-27 Stats Chippac Ltd. Semiconductor system with fine pitch lead fingers and method of manufacturing thereof
US7731078B2 (en) * 2004-11-13 2010-06-08 Stats Chippac Ltd. Semiconductor system with fine pitch lead fingers
US7701049B2 (en) * 2007-08-03 2010-04-20 Stats Chippac Ltd. Integrated circuit packaging system for fine pitch substrates
EP2486569B1 (de) 2009-10-09 2019-11-20 Semiconductor Energy Laboratory Co., Ltd. Schieberegister und anzeigevorrichtung
JP6408372B2 (ja) * 2014-03-31 2018-10-17 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置及びその駆動制御方法、並びに、電子機器
RU2654819C1 (ru) * 2017-04-26 2018-05-22 Федеральное государственное бюджетное образовательное учреждение высшего образования "ДАГЕСТАНСКИЙ ГОСУДАРСТВЕННЫЙ УНИВЕРСИТЕТ" Способ изготовления полупроводниковых структур
RU2733924C1 (ru) * 2020-01-14 2020-10-08 Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) Способ изготовления сверхмелких переходов

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3608189A (en) * 1970-01-07 1971-09-28 Gen Electric Method of making complementary field-effect transistors by single step diffusion
US3673679A (en) * 1970-12-01 1972-07-04 Texas Instruments Inc Complementary insulated gate field effect devices
US3928225A (en) * 1971-04-08 1975-12-23 Semikron Gleichrichterbau Glass forming mixture with boron as the doping material for producing conductivity zones in semiconductor bodies by means of diffusion
US3837873A (en) * 1972-05-31 1974-09-24 Texas Instruments Inc Compositions for use in forming a doped oxide film
US3789023A (en) * 1972-08-09 1974-01-29 Motorola Inc Liquid diffusion dopant source for semiconductors
JPS53135263A (en) * 1977-04-28 1978-11-25 Nec Corp Production of semiconductor device
JPS558818A (en) * 1978-07-03 1980-01-22 Sumitomo Jukikai Envirotec Kk Washing of precipitated sand in waste water treatment
US4355454A (en) * 1979-09-05 1982-10-26 Texas Instruments Incorporated Coating device with As2 -O3 -SiO2
US4455325A (en) * 1981-03-16 1984-06-19 Fairchild Camera And Instrument Corporation Method of inducing flow or densification of phosphosilicate glass for integrated circuits
JPS57194525A (en) * 1981-05-26 1982-11-30 Fujitsu Ltd Manufacture of semiconductor device
US4571366A (en) * 1982-02-11 1986-02-18 Owens-Illinois, Inc. Process for forming a doped oxide film and doped semiconductor
US4433008A (en) * 1982-05-11 1984-02-21 Rca Corporation Doped-oxide diffusion of phosphorus using borophosphosilicate glass
US4521441A (en) * 1983-12-19 1985-06-04 Motorola, Inc. Plasma enhanced diffusion process
JPH0719759B2 (ja) * 1984-09-13 1995-03-06 セイコーエプソン株式会社 半導体装置の製造方法
US4606114A (en) * 1984-08-29 1986-08-19 Texas Instruments Incorporated Multilevel oxide as diffusion source
US4603468A (en) * 1984-09-28 1986-08-05 Texas Instruments Incorporated Method for source/drain self-alignment in stacked CMOS
US4628589A (en) * 1984-09-28 1986-12-16 Texas Instruments Incorporated Method for fabricating stacked CMOS structures
JPS6260220A (ja) * 1985-09-09 1987-03-16 Seiko Epson Corp 半導体装置の製造方法
US4661177A (en) * 1985-10-08 1987-04-28 Varian Associates, Inc. Method for doping semiconductor wafers by rapid thermal processing of solid planar diffusion sources
GB8527062D0 (en) * 1985-11-02 1985-12-04 Plessey Co Plc Mos transistor manufacture
JPS62216322A (ja) * 1986-03-18 1987-09-22 Fujitsu Ltd 半導体装置の製造方法
JPH0748516B2 (ja) * 1986-09-26 1995-05-24 アメリカン テレフォン アンド テレグラフ カムパニー 埋没導電層を有する誘電的に分離されたデバイスの製造方法
JPS648615A (en) * 1987-06-30 1989-01-12 Nec Corp Manufacture of semiconductor device
JPS6484644A (en) * 1987-09-28 1989-03-29 Oki Electric Ind Co Ltd Manufacture of semiconductor element
JPH01100973A (ja) * 1987-10-14 1989-04-19 Ricoh Co Ltd 半導体装置の製造方法
JPH01123417A (ja) * 1987-11-07 1989-05-16 Mitsubishi Electric Corp 半導体装置の製造方法
JPH01173755A (ja) * 1987-12-28 1989-07-10 Mitsubishi Electric Corp 半導体装置の製造方法
US4830974A (en) * 1988-01-11 1989-05-16 Atmel Corporation EPROM fabrication process
US4891331A (en) * 1988-01-21 1990-01-02 Oi-Neg Tv Products, Inc. Method for doping silicon wafers using Al2 O3 /P2 O5 composition
JPH01194416A (ja) * 1988-01-29 1989-08-04 Sharp Corp 半導体装置の製造方法
JPH01283828A (ja) * 1988-05-10 1989-11-15 Seiko Epson Corp 半導体装置の製造方法
JPH027558A (ja) * 1988-06-27 1990-01-11 Matsushita Electron Corp 半導体装置およびその製造方法
JPH0287567A (ja) * 1988-09-26 1990-03-28 Hitachi Ltd 半導体装置の製造方法
JPH02188914A (ja) * 1989-01-17 1990-07-25 Seiko Instr Inc 半導体装置の製造方法
US5047357A (en) * 1989-02-03 1991-09-10 Texas Instruments Incorporated Method for forming emitters in a BiCMOS process
US4962049A (en) * 1989-04-13 1990-10-09 Applied Materials, Inc. Process for the plasma treatment of the backside of a semiconductor wafer
JP2845934B2 (ja) * 1989-04-26 1999-01-13 株式会社日立製作所 半導体集積回路装置の製造方法
US5024959A (en) * 1989-09-25 1991-06-18 Motorola, Inc. CMOS process using doped glass layer
JPH03218025A (ja) * 1990-01-23 1991-09-25 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
US5116778A (en) * 1990-02-05 1992-05-26 Advanced Micro Devices, Inc. Dopant sources for cmos device

Also Published As

Publication number Publication date
JP3466244B2 (ja) 2003-11-10
DE69327145D1 (de) 2000-01-05
JPH06204159A (ja) 1994-07-22
EP0594339A1 (de) 1994-04-27
EP0594339B1 (de) 1999-12-01
US5340770A (en) 1994-08-23

Similar Documents

Publication Publication Date Title
DE69327145T2 (de) Herstellungsverfahren für ein CMOS-Bauteil
DE69130777D1 (de) Herstellungsverfahren für Mikrolinsen
DE69512282D1 (de) Herstellungsverfahren für ein mikromechanisches Element
DE69309064T2 (de) Filtervorrichtung für ein tracheostoma
DE59308767D1 (de) Halterung für ein zielfernrohr
DE69408549D1 (de) Gehäuse für ein Halbleiterbauelement
DE69026242T2 (de) Korrekturvorrichtung für ein teilchengeladenes Strahlgerät
DE69117905T2 (de) Herstellungsverfahren für Alkoxyphthalocyanine
DE69207949D1 (de) Übersetzungsgetriebe für ein Fahrrad
DE69606494T2 (de) Herstellungsverfahren für Drucktasten
DE69324179D1 (de) Herstellungsverfahren für ein lichtempfindlicher elektrofotografischer Gegenstand
DE69220312T2 (de) Herstellungsverfahren für oxidischen supraleitenden film
DE69518684T2 (de) Herstellungsverfahren für ein Feldeffekt-Halbleiterbauelement
DE69500586T2 (de) Herstellungsverfahren für ein Halbleiter-Bauelement zur Speicherung mehrerer Zustände
DE69602791T2 (de) Herstellungsverfahren für eine Abdeckung
DE69516097T2 (de) Ein Beschichtungsverfahren
DE69226930T2 (de) Herstellungprozess für polyolefine
DE69301450D1 (de) Herstellungsverfahren für mikromechanisches Element
DE69513405D1 (de) Vorrichtung für ein gerüst
DE69430019D1 (de) Herstellungsverfahren für ein Leiterrahmen-Material
DE69329928D1 (de) Herstellungsverfahren für integrierten Schaltkreis
DE69011865T2 (de) Reinigungsvorrichtung für ein Filterelement.
DE69127819D1 (de) Reinigungsvorrichtung für ein Glasdach
DE9321180U1 (de) Einrichtung für ein Spannfutter
DE9405979U1 (de) Betätigungsvorrichtung für ein Verschlußgetriebe

Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HYNIX SEMICONDUCTOR INC., ICHON, KYONGGI, KR

Owner name: NCR INTERNATIONAL, INC., DAYTON, OHIO, US

8339 Ceased/non-payment of the annual fee