JP4964780B2 - ワイヤボンド相互接続、半導体パッケージ、および、ワイヤボンド相互接続の形成方法 - Google Patents
ワイヤボンド相互接続、半導体パッケージ、および、ワイヤボンド相互接続の形成方法 Download PDFInfo
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- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
Claims (15)
- ダイ上のダイパッドと、底部よりも頂部が小さい台形状の横断面を有するリードフィンガーとの間のワイヤボンド相互接続であって、前記リードフィンガーのボンドサイト上のサポート台座と、ダイパッド上のボールボンドと、前記サポート台座上のスティッチボンドとを備え、当該サポート台座は、当該リードフィンガーのみによって支持されるとともに、前記リードフィンガーの頂部にボンドされ、前記リードフィンガーの底部から離れている、ことを特徴とするワイヤボンド相互接続。
- ボンドサイトにおいてリードフィンガーは、サポート台座の径より狭くなっていることを特徴とする請求項1に記載のワイヤボンド相互接続。
- ボンドサイトにおいてリードフィンガーは、サポート台座の径より狭い平坦部を備えることを特徴とする請求項1に記載のワイヤボンド相互接続。
- ボンドサイトにおいてリードフィンガーの断面は、ベースと平坦部との間に傾斜した側面を備える略台形状の外観を有することを特徴とする請求項1に記載のワイヤボンド相互接続。
- ボンドサイトにおいてリードフィンガーは、ベースと、平坦部へ向けて集束する傾斜した側面を備え、サポート台座は、傾斜した側面の少なくとも1つについての少なくとも上部に一致するように変形することを特徴とする請求項1に記載のワイヤボンド相互接続。
- 複数のワイヤボンドによって基板にマウントされると共に電気的に接続されるダイを備える半導体パッケージであって、各前記ワイヤボンドは、前記ダイ上のパッドへボンドされるワイヤボールと、底部よりも頂部が小さい台形状の横断面を有するリードフィンガー上の、ボンドサイトの上のサポート台座へボンドされるスティッチとを備え、当該サポート台座は、当該リードフィンガーのみによって支持され、前記リードフィンガーの底部から離れていることを特徴とする半導体パッケージ。
- ボンドサイトにおいてリードフィンガーの幅は、サポート台座の径より小さいことを特徴とする請求項6に記載の半導体パッケージ。
- リードフィンガーボンドピッチは、100μmより小さいことを特徴とする請求項6に記載の半導体パッケージ。
- リードフィンガーボンドピッチは、ダイパッドピッチと同じであることを特徴とする請求項6に記載の半導体パッケージ。
- パッケージ基板は、2段の基板であり、各段は、複数のリードフィンガーを備え、第1段及び第2段のリードフィンガーは、前記2段の基板についてのリードフィンガーピッチが基板の各段についてのリードフィンガーピッチの半分となるように交互に配列されていることを特徴とする請求項6に記載の半導体パッケージ。
- 半導体ダイと基板との間のワイヤボンド相互接続を形成する方法であって、パターン付けされた配線を有する基板が底部よりも頂部が小さい台形状の横断面を有するリードフィンガーを備え、当該底部は当該基板の第1面上にあり、当該基板の第1面のダイマウント部に取付けられ、アクティブ面を基板から離れた方向へ向けられるダイを供給する工程と、リードフィンガーのボンドサイト上にサポート台座を形成する工程と、ダイパッド上に第1ボンドを形成する工程と、サポート台座上に第2ボンドを成形する工程とを備え、当該サポート台座は当該リードフィンガーによってのみ支持されるとともに、前記リードフィンガーの頂部にボンドされ、当該基板から離れている、ことを特徴とする方法。
- 第1ボンドは、ボールボンドを備えることを特徴とする請求項11に記載の方法。
- 第2ボンドは、スティッチボンドであることを特徴とする請求項11に記載の方法。
- サポート台座は、リードフィンガーへボンドされることを特徴とする請求項11に記載の方法。
- サポート台座は、スタッドバンピング操作にて形成されることを特徴とする請求項11に記載の方法。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US62765004P | 2004-11-12 | 2004-11-12 | |
| US60/627,650 | 2004-11-12 | ||
| PCT/US2005/041116 WO2006053277A2 (en) | 2004-11-12 | 2005-11-14 | Wire bond interconnection |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008520111A JP2008520111A (ja) | 2008-06-12 |
| JP2008520111A5 JP2008520111A5 (ja) | 2008-12-25 |
| JP4964780B2 true JP4964780B2 (ja) | 2012-07-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007541391A Expired - Lifetime JP4964780B2 (ja) | 2004-11-12 | 2005-11-14 | ワイヤボンド相互接続、半導体パッケージ、および、ワイヤボンド相互接続の形成方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (4) | US7453156B2 (ja) |
| JP (1) | JP4964780B2 (ja) |
| KR (1) | KR101227228B1 (ja) |
| TW (1) | TWI368974B (ja) |
| WO (1) | WO2006053277A2 (ja) |
Families Citing this family (34)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7868468B2 (en) * | 2004-11-12 | 2011-01-11 | Stats Chippac Ltd. | Wire bonding structure and method that eliminates special wire bondable finish and reduces bonding pitch on substrates |
| JP4964780B2 (ja) * | 2004-11-12 | 2012-07-04 | スタッツ・チップパック・インコーポレイテッド | ワイヤボンド相互接続、半導体パッケージ、および、ワイヤボンド相互接続の形成方法 |
| US8519517B2 (en) * | 2004-11-13 | 2013-08-27 | Stats Chippac Ltd. | Semiconductor system with fine pitch lead fingers and method of manufacturing thereof |
| US7731078B2 (en) * | 2004-11-13 | 2010-06-08 | Stats Chippac Ltd. | Semiconductor system with fine pitch lead fingers |
| EP3479844B1 (en) | 2005-04-15 | 2023-11-22 | MacroGenics, Inc. | Covalent diabodies and uses thereof |
| TW200642012A (en) * | 2005-05-17 | 2006-12-01 | Advanced Semiconductor Eng | Chip package and wire bonding process thereof |
| US20070018292A1 (en) * | 2005-07-22 | 2007-01-25 | Sehat Sutardja | Packaging for high speed integrated circuits |
| US20070026573A1 (en) * | 2005-07-28 | 2007-02-01 | Aminuddin Ismail | Method of making a stacked die package |
| US7863099B2 (en) * | 2007-06-27 | 2011-01-04 | Stats Chippac Ltd. | Integrated circuit package system with overhanging connection stack |
| SG148901A1 (en) | 2007-07-09 | 2009-01-29 | Micron Technology Inc | Packaged semiconductor assemblies and methods for manufacturing such assemblies |
| US7701049B2 (en) * | 2007-08-03 | 2010-04-20 | Stats Chippac Ltd. | Integrated circuit packaging system for fine pitch substrates |
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2005
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- 2005-11-14 US US11/273,635 patent/US7453156B2/en active Active
- 2005-11-14 KR KR1020077010429A patent/KR101227228B1/ko not_active Expired - Lifetime
- 2005-11-14 TW TW094139959A patent/TWI368974B/zh not_active IP Right Cessation
- 2005-11-14 WO PCT/US2005/041116 patent/WO2006053277A2/en not_active Ceased
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|---|---|
| US20080135997A1 (en) | 2008-06-12 |
| TW200623373A (en) | 2006-07-01 |
| JP2008520111A (ja) | 2008-06-12 |
| US20110266700A1 (en) | 2011-11-03 |
| US7986047B2 (en) | 2011-07-26 |
| TWI368974B (en) | 2012-07-21 |
| US20100225008A1 (en) | 2010-09-09 |
| US7745322B2 (en) | 2010-06-29 |
| US8129263B2 (en) | 2012-03-06 |
| KR101227228B1 (ko) | 2013-01-28 |
| US7453156B2 (en) | 2008-11-18 |
| KR20070084060A (ko) | 2007-08-24 |
| WO2006053277A3 (en) | 2007-06-21 |
| US20060113665A1 (en) | 2006-06-01 |
| WO2006053277A2 (en) | 2006-05-18 |
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