DE69233225D1 - Substrat für Dünnschichtschaltung und Verfahren zur Herstellung desselben - Google Patents
Substrat für Dünnschichtschaltung und Verfahren zur Herstellung desselbenInfo
- Publication number
- DE69233225D1 DE69233225D1 DE69233225T DE69233225T DE69233225D1 DE 69233225 D1 DE69233225 D1 DE 69233225D1 DE 69233225 T DE69233225 T DE 69233225T DE 69233225 T DE69233225 T DE 69233225T DE 69233225 D1 DE69233225 D1 DE 69233225D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing
- thin film
- same
- circuit substrate
- film circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/024—Dielectric details, e.g. changing the dielectric material around a transmission line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/145—Organic substrates, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/07—Electric details
- H05K2201/0707—Shielding
- H05K2201/0715—Shielding provided by an outer layer of PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1184—Underetching, e.g. etching of substrate under conductors or etching of conductor under dielectrics; Means for allowing or controlling underetching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S428/00—Stock material or miscellaneous articles
- Y10S428/901—Printed circuit
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/31504—Composite [nonstructural laminate]
- Y10T428/31678—Of metal
- Y10T428/31681—Next to polyester, polyamide or polyimide [e.g., alkyd, glue, or nylon, etc.]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1635591 | 1991-02-07 | ||
JP1635591A JP2500235B2 (ja) | 1991-02-07 | 1991-02-07 | 薄膜回路基板及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69233225D1 true DE69233225D1 (de) | 2003-11-13 |
DE69233225T2 DE69233225T2 (de) | 2004-07-01 |
Family
ID=11914045
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE1992633225 Expired - Fee Related DE69233225T2 (de) | 1991-02-07 | 1992-02-06 | Substrat für Dünnschichtschaltung und Verfahren zur Herstellung desselben |
Country Status (4)
Country | Link |
---|---|
US (2) | US5298114A (de) |
EP (1) | EP0502614B1 (de) |
JP (1) | JP2500235B2 (de) |
DE (1) | DE69233225T2 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5403437A (en) * | 1993-11-05 | 1995-04-04 | Texas Instruments Incorporated | Fluorosurfactant in photoresist for amorphous "Teflon" patterning |
US5447600A (en) * | 1994-03-21 | 1995-09-05 | Texas Instruments | Polymeric coatings for micromechanical devices |
JP2560637B2 (ja) * | 1994-04-28 | 1996-12-04 | 日本電気株式会社 | 電界効果トランジスタ及びその製造方法 |
WO1995034096A1 (en) * | 1994-06-03 | 1995-12-14 | E.I. Du Pont De Nemours And Company | Fluoropolymer protectant layer for high temperature superconductor film and photo-definition thereof |
JPH0855913A (ja) * | 1994-06-07 | 1996-02-27 | Texas Instr Inc <Ti> | サブミクロン相互接続の選択的空隙充填方法 |
US6053617A (en) * | 1994-09-23 | 2000-04-25 | Texas Instruments Incorporated | Manufacture method for micromechanical devices |
AU5769300A (en) * | 1999-06-29 | 2001-01-31 | Sun Microsystems, Inc. | Method and apparatus for adjusting electrical characteristics of signal traces in layered circuit boards |
US7658709B2 (en) * | 2003-04-09 | 2010-02-09 | Medtronic, Inc. | Shape memory alloy actuators |
JP4969993B2 (ja) * | 2006-11-01 | 2012-07-04 | 日本メクトロン株式会社 | 多層フレキシブルプリント配線板およびその製造法 |
JP2013084842A (ja) * | 2011-10-12 | 2013-05-09 | Fujitsu Ltd | 配線構造及びその製造方法 |
US11574862B2 (en) | 2019-04-23 | 2023-02-07 | Intel Corporation | Optimal signal routing performance through dielectric material configuration designs in package substrate |
US20210028101A1 (en) * | 2019-07-25 | 2021-01-28 | Intel Corporation | Embedded patch for local material property modulation |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS542667A (en) * | 1977-06-08 | 1979-01-10 | Fujitsu Ltd | Manufacture of semiconductor device |
US4689110A (en) * | 1983-12-22 | 1987-08-25 | Trw Inc. | Method of fabricating multilayer printed circuit board structure |
US4647508A (en) * | 1984-07-09 | 1987-03-03 | Rogers Corporation | Flexible circuit laminate |
JPS6154674A (ja) * | 1984-08-25 | 1986-03-18 | Fujitsu Ltd | 超高周波集積回路装置 |
US4758476A (en) * | 1984-12-12 | 1988-07-19 | Hitachi Chemical Company, Ltd. | Polyimide precursor resin composition and semiconductor device using the same |
JPS62188399A (ja) * | 1986-02-14 | 1987-08-17 | 日本電気株式会社 | セラミツク配線基板 |
US4931354A (en) * | 1987-11-02 | 1990-06-05 | Murata Manufacturing Co., Ltd. | Multilayer printed circuit board |
JPH01298764A (ja) * | 1988-05-26 | 1989-12-01 | Nec Corp | 半導体記憶装置 |
DE69031357T2 (de) * | 1989-04-21 | 1998-04-02 | Nec Corp | Halbleiteranordnung mit Mehrschichtleiter |
US4970106A (en) * | 1989-06-02 | 1990-11-13 | International Business Machines Corporation | Thin film multilayer laminate interconnection board |
US5227013A (en) * | 1991-07-25 | 1993-07-13 | Microelectronics And Computer Technology Corporation | Forming via holes in a multilevel substrate in a single step |
-
1991
- 1991-02-07 JP JP1635591A patent/JP2500235B2/ja not_active Expired - Fee Related
-
1992
- 1992-02-06 DE DE1992633225 patent/DE69233225T2/de not_active Expired - Fee Related
- 1992-02-06 EP EP19920300985 patent/EP0502614B1/de not_active Expired - Lifetime
-
1993
- 1993-03-29 US US08/038,272 patent/US5298114A/en not_active Expired - Lifetime
-
1994
- 1994-09-07 US US08/302,085 patent/US6110568A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0502614B1 (de) | 2003-10-08 |
DE69233225T2 (de) | 2004-07-01 |
JPH04255292A (ja) | 1992-09-10 |
US5298114A (en) | 1994-03-29 |
US6110568A (en) | 2000-08-29 |
EP0502614A3 (en) | 1993-01-20 |
JP2500235B2 (ja) | 1996-05-29 |
EP0502614A2 (de) | 1992-09-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |