DE69221109T2 - Digital gesteuertes CMOS-Verzögerungsgatter - Google Patents

Digital gesteuertes CMOS-Verzögerungsgatter

Info

Publication number
DE69221109T2
DE69221109T2 DE69221109T DE69221109T DE69221109T2 DE 69221109 T2 DE69221109 T2 DE 69221109T2 DE 69221109 T DE69221109 T DE 69221109T DE 69221109 T DE69221109 T DE 69221109T DE 69221109 T2 DE69221109 T2 DE 69221109T2
Authority
DE
Germany
Prior art keywords
channel transistor
delay gate
digitally controlled
digital
snm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69221109T
Other languages
English (en)
Other versions
DE69221109D1 (de
Inventor
Ann K Woo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69221109D1 publication Critical patent/DE69221109D1/de
Application granted granted Critical
Publication of DE69221109T2 publication Critical patent/DE69221109T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H03K2005/00065—Variable delay controlled by a digital setting by current control, e.g. by parallel current control transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69221109T 1992-01-02 1992-12-16 Digital gesteuertes CMOS-Verzögerungsgatter Expired - Fee Related DE69221109T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/815,791 US5227679A (en) 1992-01-02 1992-01-02 Cmos digital-controlled delay gate

Publications (2)

Publication Number Publication Date
DE69221109D1 DE69221109D1 (de) 1997-08-28
DE69221109T2 true DE69221109T2 (de) 1998-02-12

Family

ID=25218839

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69221109T Expired - Fee Related DE69221109T2 (de) 1992-01-02 1992-12-16 Digital gesteuertes CMOS-Verzögerungsgatter

Country Status (6)

Country Link
US (1) US5227679A (de)
EP (1) EP0550216B1 (de)
JP (1) JPH05268015A (de)
KR (1) KR930017300A (de)
AT (1) ATE155942T1 (de)
DE (1) DE69221109T2 (de)

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US6078627A (en) * 1997-12-18 2000-06-20 Advanced Micro Devices, Inc. Circuit and method for multilevel signal decoding, descrambling, and error detection
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US6377102B2 (en) * 2000-02-29 2002-04-23 Texas Instruments Incorporated Load equalization in digital delay interpolators
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US6650159B2 (en) * 2002-03-29 2003-11-18 Intel Corporation Method and apparatus for precise signal interpolation
US20050153712A1 (en) * 2004-01-08 2005-07-14 Ken Osaka Method and system for determining mobile unit location by aggregation of tagged signals from a distributed antenna system
US7405597B1 (en) * 2005-06-30 2008-07-29 Transmeta Corporation Advanced repeater with duty cycle adjustment
US7304503B2 (en) * 2004-06-08 2007-12-04 Transmeta Corporation Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability
US7173455B2 (en) 2004-06-08 2007-02-06 Transmeta Corporation Repeater circuit having different operating and reset voltage ranges, and methods thereof
JP2005353677A (ja) * 2004-06-08 2005-12-22 Fujitsu Ltd ディレイ値調整方法および半導体集積回路
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US7071747B1 (en) 2004-06-15 2006-07-04 Transmeta Corporation Inverting zipper repeater circuit
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US7814449B2 (en) * 2007-10-17 2010-10-12 International Business Machines Corporation Design structure for multiple source-single drain field effect semiconductor device and circuit
US9001811B2 (en) 2009-05-19 2015-04-07 Adc Telecommunications, Inc. Method of inserting CDMA beacon pilots in output of distributed remote antenna nodes
US8461893B2 (en) * 2011-08-16 2013-06-11 Lsi Corporation Uniform-footprint programmable multi-stage delay cell
US8536921B2 (en) 2011-08-16 2013-09-17 Lsi Corporation Uniform-footprint programmable-skew multi-stage delay cell
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US9569570B2 (en) 2015-04-01 2017-02-14 Freescale Semiconductor, Inc. Configurable delay cell
CN107623516A (zh) * 2016-07-13 2018-01-23 北京捷联微芯科技有限公司 一种数字调节输出信号交叉电压的方法及电路
US10447270B2 (en) * 2017-12-08 2019-10-15 Rambus Inc. Low power logic circuitry
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CN115694438B (zh) * 2023-01-04 2023-03-17 华中科技大学 一种轻量级宽电压域时序错误检测单元
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10141939B4 (de) * 2000-08-23 2011-08-11 Samsung Electronics Co., Ltd., Kyonggi Flip-Flop-Schaltung zur taktsignalabhängigen Datenpufferung und diese enthaltender Signalhöhenkomparator

Also Published As

Publication number Publication date
DE69221109D1 (de) 1997-08-28
EP0550216A1 (de) 1993-07-07
ATE155942T1 (de) 1997-08-15
US5227679A (en) 1993-07-13
JPH05268015A (ja) 1993-10-15
KR930017300A (ko) 1993-08-30
EP0550216B1 (de) 1997-07-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee