CN117613005B - 一种混合型cmos器件及其制作方法 - Google Patents

一种混合型cmos器件及其制作方法 Download PDF

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CN117613005B
CN117613005B CN202410092726.6A CN202410092726A CN117613005B CN 117613005 B CN117613005 B CN 117613005B CN 202410092726 A CN202410092726 A CN 202410092726A CN 117613005 B CN117613005 B CN 117613005B
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余毅
李彦庆
郭同健
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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Abstract

本发明涉及半导体器件制造技术领域，具体涉及一种混合型CMOS器件及其制作方法，制作步骤包括：(1)选取硅片作为衬底，经过化学清洗；(2)使用掩膜技术在衬底表面覆盖一层光刻胶，在p型区域和n型区域注入掺杂剂，快速退火使掺杂的材料与硅晶片结合；(3)在整个硅衬底上生长一层绝缘性氧化层；(4)利用光刻技术在绝缘氧化层上形成多晶硅门电极；(5)在整个器件上沉积金属层；(6)将多余的金属层和绝缘层刻蚀掉。本申请提出的混合型CMOS器件制作方法可以进一步减小器件的尺寸和功耗，实现更小的芯片面积和更高的集成度，制得的混合型CMOS器件具有更广泛的应用领域、更高的集成度和功能性、较低的功耗。

Description

一种混合型CMOS器件及其制作方法
技术领域
本发明涉及半导体器件制造技术领域，具体涉及一种混合型CMOS器件及其制作方法。
背景技术
混合型CMOS芯片（Complementary Metal Oxide Semiconductor）是一种结合了模拟信号和数字信号处理功能的集成电路芯片，译为互补-金属-氧化物-半导体存储器。CMOS集成电路是将N沟道MOS晶体管和P沟道MOS晶体管同时用于一个集成电路中，它在同一芯片上同时包含了模拟电路和数字电路的特性，使得芯片能够处理模拟信号和数字信号的混合输入输出；
在混合型CMOS器件中，n型区域和p型区域是指完全沟道长度（L）的一部分，它们用于构成MOSFET晶体管的源极和漏极区域。n型（通常用于nMOSFET晶体管）区域是掺杂有五价磷（Phosphorus）等掺杂物的硅材料，这些掺杂物会提供额外的自由电子，使得该区域具有负电荷，从而形成n型导电性，当输入信号为高电平时，n型区域之间形成导电通路；p型（通常用于pMOSFET晶体管）区域是掺杂有三价硼（Boron）等掺杂物的硅材料，这些掺杂物会提供额外的“空穴”，使得该区域具有正电荷，从而形成p型导电性，当输入信号为低电平时，p型区域之间形成导电通路。
而现有技术中许多混合型CMOS器件的尺寸比例设计不当，尺寸比例不合理可能导致器件的静态功耗（即漏电流）失衡，如果N型区域过大，将导致静态功耗增加；而如果P型区域过大，将导致驱动能力不足。
发明内容
针对上述现有技术中的不足，本发明提供了一种调节n型区域和p型区域以提高CMOS器件的集成度以及降低功耗和尺寸的混合型CMOS器件制作方法。
本发明的目的采用以下技术方案来实现：
一种混合型CMOS器件的制作方法，包括以下制备步骤：
(1)选取硅片作为衬底，经过化学清洗，除去所述衬底的表面的杂质和氧化层；
(2)在所述衬底的表面覆盖一层光刻胶，将掩膜与所述衬底对准，使用光刻机进行曝光；
(3)在所述衬底的p型区域和n型区域注入掺杂剂，快速退火使掺杂的材料与硅晶片结合，使用有机溶剂去除残留的光刻胶；
(4)使用化学气相沉积法在所述硅衬底上生长一层绝缘性氧化层；
(5)利用光刻技术在所述衬底的绝缘氧化层上形成多晶硅门电极；
(6)在整个器件上沉积金属层；
(7)将所述器件上多余的金属层和绝缘层刻蚀掉，形成器件的导线和联系孔。
优选地，所述步骤（1）中，化学清洗具体包括：将硅片浸泡在碱性溶液中，取出后用去离子水清洗，再将硅片浸泡在酸性溶液中，取出后用去离子水清洗。
更优选地，所述碱性溶液选自浓氢氧化钠或浓氢氧化铵，所述酸性溶液选自浓硝酸或浓氢氟酸，所述浸泡时间为10~15min，所述去离子水温度为40~50℃，所述去离子水清洗时间为5~8min。
优选地，所述步骤（3）中，快速退火温度为800~1100℃，高温结束后迅速将加热后的所述衬底冷却至常温。
优选地，所述步骤（3）中，所述衬底的p型区域以硼作为掺杂剂，所述衬底n型区域的掺杂剂选自磷或砷中的一种。
更优选地，所述CMOS器件逻辑门为与门时，Dn：Dp=1~1.5：1，所述CMOS器件逻辑门为或门时，Dn：Dp=1：2~3，其中Dn表示n型区域的宽度，Dp表示p型区域的宽度。
不同类型的逻辑门（如与门、或门、非门）的布局和结构会对p型和n型区域的大小有不同的要求。非门仅包含一个晶体管，因此对区域尺寸的要求较小，p型和n型区域都较小；与门需要n型区域作为输入和输出，通常需要多个串联的MOS晶体管，因此对于n型区域来说，需要具有较高的导通能力，因此n型区域较大，而p型区域的尺寸较小；或门则需要p型区域作为输入和输出，通常需要多个并联的MOS晶体管，因此对于p型区域来说，需要具有较高的导通能力，因此p型区域较大，而n型区域的尺寸较小。
优选地，所述步骤（4）中，绝缘性氧化层为SiO2。
优选地，所述步骤（5）中，多晶硅门电极层厚度为60~90nm，多晶硅门宽度和厚度的比例为1~2：1，多晶硅门电极层长度的计算公式为：
其中，L表示多晶硅门电极层长度，W表示器件宽度，e表示电场强度，C表示电容。
一种根据混合型CMOS器件及其制作方法制得的混合型CMOS器件。
优选地，所述一种混合型CMOS器件，用于图像传感、模拟信号处理或无线通信领域。
有益效果：
1、本申请根据不同逻辑门在工作过程中需要不同的驱动电流，合理设置n型和p型区域宽度的比例，对CMOS器件的n型和p型区域宽度进行限定，优化CMOS器件的功耗，可以平衡n型和p型晶体管的工作速度，提高整体的逻辑门响应时间。
2、本申请根据器件宽度、电场强度以及电容计算多晶硅门电极的长度，通过控制多晶硅门电极的长度提高晶体管的驱动能力，信号传输的路径较短时，减小了电荷积累效应，电荷的移动时间更短，从而使得晶体管的开启和关闭速度更快，降低互连延迟，n型FET（n型场效应晶体管）和p型FET（p型场效应晶体管）的工作机制和性能不同，通过调整多晶硅门电极的长度，可以实现更好的电流控制和性能优化，提高整个CMOS器件的工作速度。
3、本申请设计通过优化器件的工艺，进一步减小器件的尺寸和功耗，缩短芯片设计时长，在短时间内实现更小的芯片面积和更高的集成度，混合型CMOS器件具有更广泛的应用领域、更高的集成度和功能性、较低的功耗。
附图说明
利用附图对本发明作进一步说明，但附图中的实施例不构成对本发明的任何限制，对于本领域的普通技术人员，在不付出创造性劳动的前提下，还可以根据以下附图获得其它的附图。
图1为混合型CMOS器件的制作方法流程图。
具体实施方式
发明人发现，现有技术形成的混合型CMOS器件的尺寸比例设计不当，导致器件的静态功耗（即漏电流）失衡，针对上述原因，本发明提供一种混合型CMOS器件及其制作方法，通过优化器件的工艺，减小器件的尺寸和功耗，缩短芯片设计时长，在短时间内实现更小的芯片面积和更高的集成度，混合型CMOS器件具有更广泛的应用领域、更高的集成度和功能性、较低的功耗。
一种混合型CMOS器件的制作方法，包括以下制备步骤：
(1)选取硅片作为衬底，将硅片浸泡在浓氢氧化钠或浓氢氧化铵中10~15min，取出后用40~50℃的去离子水清洗5~8min，再将硅片浸泡在浓硝酸或浓氢氟酸中10~15min，取出后用40~50℃的去离子水清洗5~8min，除去所述衬底的表面的杂质和氧化层；
(2)在所述衬底的表面覆盖一层光刻胶，将掩膜与所述衬底对准，使用光刻机进行曝光；
(3)当CMOS器件逻辑门为与门时，Dn：Dp=1~1.5：1，所述CMOS器件逻辑门为或门时，Dn：Dp=1：2~3，其中Dn表示n型区域的宽度，Dp表示p型区域的宽度，在衬底的p型区域注入硼掺杂剂，在衬底的n型区域注入磷或砷掺杂剂，快速退火使掺杂的材料与硅晶片结合，快速退火温度为800~1100℃，高温结束后迅速将加热后的所述衬底冷却至常温，冷却结束后使用有机溶剂去除残留的光刻胶；
(4)使用化学气相沉积法在所述硅衬底上生长一层SiO2绝缘性氧化层；
(5)利用光刻技术在所述衬底的绝缘氧化层上形成多晶硅门电极，多晶硅门电极层厚度为60~90nm，多晶硅门宽度和厚度的比例为1~2：1，多晶硅门电极层长度根据公式计算，其中，L表示多晶硅门电极层长度，W表示器件宽度，e表示电场强度，C表示电容；
(6)在整个器件上沉积金属层；
(7)将所述器件上多余的金属层和绝缘层刻蚀掉，形成器件的导线和联系孔。
为了更清楚的说明本发明，对本发明的技术特征、目的和有益效果有更加清楚的理解，现对本发明的技术方案进行以下详细说明，但不能理解为对本发明的可实施范围的限定。
以下实施例中所用的原料、试剂或装置如无特殊说明，均可从常规商业途径得到，或者可以通过现有已知方法得到。
结合以下实施例对本发明作进一步说明。
实施例1
一种混合型CMOS器件及其制作方法，包括以下制备步骤：
(1)选取硅片作为衬底，将衬底浸泡在浓氢氧化钠溶液中10min，取出后用40℃的去离子水清洗5min，再将硅片浸泡在浓硝酸溶液中10min，取出后用40℃的去离子水清洗5min，除去表面杂质和氧化层；
(2)在衬底的表面覆盖一层光刻胶，将掩膜与衬底对准，使用光刻机进行曝光；
(3)当CMOS器件逻辑门为与门时，Dn：Dp=1：1，当CMOS器件逻辑门为或门时，Dn：Dp=1：2，其中Dn表示n型区域的宽度，Dp表示p型区域的宽度，在衬底的p型区域注入硼掺杂剂，在衬底的n型区域注入磷掺杂剂，注入掺杂剂后快速退火使掺杂的材料与硅晶片结合，快速退火温度为800℃，高温结束后迅速将加热后的衬底冷却至常温，使用有机溶剂去除衬底上残留的光刻胶；
(4)使用化学气相沉积法在整个硅衬底上生长一层SiO2；
(5)利用光刻技术在衬底的绝缘氧化层上形成厚度为60nm的多晶硅门电极，多晶硅门宽度和厚度的比例为1：1，根据计算公式计算出多晶硅门电极层的长度；
(6)在整个器件上沉积金属层；
(7)将衬底上多余的金属层和绝缘层刻蚀掉，形成器件的导线和联系孔，最后进行封装。
实施例2
(1)选取硅片作为衬底，将衬底浸泡在浓氢氧化钠溶液中15min，取出后用50℃的去离子水清洗8min，再将衬底浸泡在浓硝酸溶液中15min，取出后用50℃的去离子水清洗8min，除去衬底表面的杂质和氧化层；
(2)在衬底的表面覆盖一层光刻胶，将掩膜与衬底对准，使用光刻机进行曝光；
(3)当CMOS器件逻辑门为与门时，Dn：Dp=1.5：1，当CMOS器件逻辑门为或门时，Dn：Dp=1：3，其中Dn表示n型区域的宽度，Dp表示p型区域的宽度，在衬底的p型区域注入硼掺杂剂，在衬底的n型区域注入磷掺杂剂，注入掺杂剂后快速退火使掺杂的材料与硅晶片结合，快速退火温度为1100℃，高温结束后迅速将加热后的衬底冷却至常温，使用有机溶剂去除衬底上残留的光刻胶；
(4)使用化学气相沉积法在整个硅衬底上生长一层SiO2；
(5)利用光刻技术在衬底的绝缘氧化层上形成厚度为90nm的多晶硅门电极，多晶硅门宽度和厚度的比例为2：1，根据计算公式计算出多晶硅门电极层的长度；
(6)在整个器件上沉积金属层；
(7)将衬底上多余的金属层和绝缘层刻蚀掉，形成器件的导线和联系孔，最后进行封装。
最后应当说明的是，以上实施例仅用以说明本发明的技术方案，而非对本发明保护范围的限制，尽管参照较佳实施例对本发明作了详细地说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明技术方案的实质和范围。

Claims (8)

1.一种混合型CMOS器件的制作方法，其特征在于，包括以下制备步骤：
(1)选取硅片作为衬底，经过化学清洗，除去所述衬底的表面的杂质和氧化层；
(2)在所述衬底的表面覆盖一层光刻胶，将掩膜与所述衬底对准，使用光刻机进行曝光；
(3)在所述衬底的p型区域和n型区域注入掺杂剂，快速退火使掺杂的材料与硅晶片结合，使用有机溶剂去除残留的光刻胶；
(4)使用化学气相沉积法在所述衬底上生长一层绝缘性氧化层；
(5)利用光刻技术在所述衬底的绝缘氧化层上形成多晶硅门电极，多晶硅门电极层厚度为60~90nm，多晶硅门宽度和厚度的比例为1~2：1，多晶硅门电极层长度的计算公式为：，其中，L表示多晶硅门电极层长度，W表示器件宽度，e表示电场强度，C表示电容；
(6)在整个器件上沉积金属层；
(7)将所述器件上多余的金属层和绝缘层刻蚀掉，形成器件的导线和联系孔；所述CMOS器件逻辑门为与门时，Dn：Dp=1~1.5：1，所述CMOS器件逻辑门为或门时，Dn：Dp=1：2~3，其中Dn表示n型区域的宽度，Dp表示p型区域的宽度。
2.根据权利要求1所述的一种混合型CMOS器件的制作方法，其特征在于，所述步骤（1）中，化学清洗具体包括：将硅片浸泡在碱性溶液中，取出后用去离子水清洗，再将硅片浸泡在酸性溶液中，取出后用去离子水清洗。
3.根据权利要求2所述的一种混合型CMOS器件的制作方法，其特征在于，所述碱性溶液选自浓氢氧化钠或浓氢氧化铵，所述酸性溶液选自浓硝酸或浓氢氟酸，所述浸泡时间为10~15min，所述去离子水温度为40~50℃，所述去离子水清洗时间为5~8min。
4.根据权利要求1所述的一种混合型CMOS器件的制作方法，其特征在于，所述步骤（3）中，快速退火温度为800~1100℃，高温结束后迅速将加热后的所述衬底冷却至常温。
5.根据权利要求1所述的一种混合型CMOS器件的制作方法，其特征在于，所述步骤（3）中，所述衬底的p型区域以硼作为掺杂剂，所述衬底n型区域的掺杂剂选自磷或砷中的一种。
6.根据权利要求1所述的一种混合型CMOS器件的制作方法，其特征在于，所述步骤（4）中，绝缘性氧化层为SiO2。
7.一种混合型CMOS器件，其特征在于，根据权利要求1-6任一项所述的制作方法制得。
8.根据权利要求7所述的混合型CMOS器件，其特征在于，用于图像传感、模拟信号处理或无线通信领域。
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