DE69220256D1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69220256D1
DE69220256D1 DE69220256T DE69220256T DE69220256D1 DE 69220256 D1 DE69220256 D1 DE 69220256D1 DE 69220256 T DE69220256 T DE 69220256T DE 69220256 T DE69220256 T DE 69220256T DE 69220256 D1 DE69220256 D1 DE 69220256D1
Authority
DE
Germany
Prior art keywords
mode
memory device
semiconductor memory
port
sam port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69220256T
Other languages
English (en)
Other versions
DE69220256T2 (de
Inventor
Tatsuo Ikawa
Shigeo Ohshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69220256D1 publication Critical patent/DE69220256D1/de
Publication of DE69220256T2 publication Critical patent/DE69220256T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/20—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
DE69220256T 1991-01-23 1992-01-23 Halbleiterspeicheranordnung Expired - Fee Related DE69220256T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3006427A JP2549209B2 (ja) 1991-01-23 1991-01-23 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69220256D1 true DE69220256D1 (de) 1997-07-17
DE69220256T2 DE69220256T2 (de) 1997-10-30

Family

ID=11638090

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69220256T Expired - Fee Related DE69220256T2 (de) 1991-01-23 1992-01-23 Halbleiterspeicheranordnung

Country Status (5)

Country Link
US (1) US5239509A (de)
EP (1) EP0496391B1 (de)
JP (1) JP2549209B2 (de)
KR (1) KR960001783B1 (de)
DE (1) DE69220256T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2768175B2 (ja) * 1992-10-26 1998-06-25 日本電気株式会社 半導体メモリ
JPH06333384A (ja) * 1993-05-19 1994-12-02 Toshiba Corp 半導体記憶装置
GB2283342B (en) * 1993-10-26 1998-08-12 Intel Corp Programmable code store circuitry for a nonvolatile semiconductor memory device
US5526311A (en) * 1993-12-30 1996-06-11 Intel Corporation Method and circuitry for enabling and permanently disabling test mode access in a flash memory device
EP0668561B1 (de) * 1994-02-22 2002-04-10 Siemens Aktiengesellschaft Flexible Fehlerkorrekturcode/Paritätsbit-Architektur
US5553238A (en) * 1995-01-19 1996-09-03 Hewlett-Packard Company Powerfail durable NVRAM testing
US5657287A (en) * 1995-05-31 1997-08-12 Micron Technology, Inc. Enhanced multiple block writes to adjacent blocks of memory using a sequential counter
US6214706B1 (en) * 1998-08-28 2001-04-10 Mv Systems, Inc. Hot wire chemical vapor deposition method and apparatus using graphite hot rods
US7120761B2 (en) 2000-12-20 2006-10-10 Fujitsu Limited Multi-port memory based on DRAM core
US20020078311A1 (en) * 2000-12-20 2002-06-20 Fujitsu Limited Multi-port memory based on DRAM core
US6920072B2 (en) * 2003-02-28 2005-07-19 Union Semiconductor Technology Corporation Apparatus and method for testing redundant memory elements
GB2403574B (en) 2003-07-03 2005-05-11 Micron Technology Inc Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
KR100655081B1 (ko) * 2005-12-22 2006-12-08 삼성전자주식회사 가변적 액세스 경로를 가지는 멀티 포트 반도체 메모리장치 및 그에 따른 방법
KR100745374B1 (ko) * 2006-02-21 2007-08-02 삼성전자주식회사 멀티포트 반도체 메모리 장치 및 그에 따른 신호 입출력방법
JP5086577B2 (ja) * 2006-07-28 2012-11-28 株式会社日立超エル・エス・アイ・システムズ 半導体装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4227244A (en) * 1978-11-30 1980-10-07 Sperry Corporation Closed loop address
JPS62277700A (ja) * 1986-05-24 1987-12-02 Hitachi Electronics Eng Co Ltd ビデオｒａｍテスト方式
JPH0760594B2 (ja) * 1987-06-25 1995-06-28 富士通株式会社 半導体記憶装置
JPH0283899A (ja) * 1988-09-20 1990-03-23 Fujitsu Ltd 半導体記憶装置
JPH02187989A (ja) * 1989-01-13 1990-07-24 Nec Corp デュアルポートメモリ
JP2953737B2 (ja) * 1990-03-30 1999-09-27 日本電気株式会社 複数ビット並列テスト回路を具備する半導体メモリ

Also Published As

Publication number Publication date
EP0496391A3 (en) 1993-09-29
JP2549209B2 (ja) 1996-10-30
DE69220256T2 (de) 1997-10-30
KR920015374A (ko) 1992-08-26
US5239509A (en) 1993-08-24
KR960001783B1 (ko) 1996-02-05
EP0496391B1 (de) 1997-06-11
EP0496391A2 (de) 1992-07-29
JPH056696A (ja) 1993-01-14

Similar Documents

Publication Publication Date Title
KR950004854B1 (ko) 반도체 메모리 장치
DE69220256D1 (de) Halbleiterspeicheranordnung
KR920013446A (ko) 블럭라이트 기능을 구비하는 반도체기억장치
KR890017706A (ko) 다이나믹형 반도체 기억장치
KR880013168A (ko) 반도체 기억장치
JPS57105897A (en) Semiconductor storage device
KR930005030A (ko) 반도체 메모리
TW331007B (en) Semiconductor memory device
KR900015154A (ko) 디-램형 집적 반도체 메모리와 그 시험방법
MY117017A (en) Four device sram cell with single bitline
KR880005623A (ko) 멀리비트 테스트모드에서 임의의 테스트패턴으로 메가비트 기억모듈을 테스트하기 위한 방법 및 장치
JPS6419584A (en) Semiconductor memory device
KR910015999A (ko) 반도체 메모리장치
KR910013285A (ko) 불휘발성 반도체메모리
EP0553788A3 (en) Semiconductor memory device incorporating redundancy memory cells having parallel test function
KR920010624A (ko) 반도체기억장치
KR960025777A (ko) 프리챠지 회로를 갖는 반도체 메모리 디바이스
EP0483723A3 (en) Semiconductor memory device with sense amplifier unit as well as data register/pointer shared between plural memory cell arrays
KR910020450A (ko) 반도체기억장치를 위한 테스트장치
EP0566153A3 (en) Semiconductor memory device having test mode
TW238387B (en) Decoding circuit for semiconductor memory device and its process
EP0285125A3 (de) Halbleiterspeicher mit einer Parallel-Eingangs-/Ausgangsschaltung
TW374931B (en) Semiconductor memory device
KR970703035A (ko) 병렬 블럭 기입 동작을 사용하여 메모리 회로를 테스팅하기 위한 방법 및 장치(A Method and Apparatus for Testing a Memory Circuit with Parallel Block Write Operation)
TW358908B (en) Data processing device

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee