KR920010617A - 반도체 기억장치 - Google Patents

반도체 기억장치 Download PDF

Info

Publication number
KR920010617A
KR920010617A KR1019910021470A KR910021470A KR920010617A KR 920010617 A KR920010617 A KR 920010617A KR 1019910021470 A KR1019910021470 A KR 1019910021470A KR 910021470 A KR910021470 A KR 910021470A KR 920010617 A KR920010617 A KR 920010617A
Authority
KR
South Korea
Prior art keywords
data
memory
levels
bits
memory cell
Prior art date
Application number
KR1019910021470A
Other languages
English (en)
Other versions
KR950002290B1 (ko
Inventor
쇼오조 사이토
Original Assignee
아오이 죠이치
가부시기가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시기가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR920010617A publication Critical patent/KR920010617A/ko
Application granted granted Critical
Publication of KR950002290B1 publication Critical patent/KR950002290B1/ko

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628Programming or writing circuits; Data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5657Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using ferroelectric storage elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음.

Description

반도체 기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예를 나타내는 회로도,
제2도는 제1도를 구체적으로 나타내는 회로도.

Claims (7)

  1. 2비트 이상의 다치의 데이타를 기억하는 것이 가능한 메모리셀이 배설된 메모리셀 어레이(11)와, 상기 1개의 메모리셀에 대응하여 복수개 설치되고, 메모리셀에서 독출된 다치의 데이타를 다치의 데이타에 대응한 복수의 레퍼런스, 레벨에 의거하여 검출하고 또 복수 비트의 기록 데이타에 대응한 프라챠지 . 레벨에 의하여 메모리셀에 데이타를 기록하는 증폭회로군(14)과, 이 증폭회로군에서 출력되는 다치의 데이타를 복수 비트의 데이타로 변환하는 동시에 복수 비트의 기록 데이타에 따라서 상기 증폭회로군을 선택하는 선택신호를 생성하는 데이타 변환회로(16)와, 이 데이타 변환회로에서 공급된 데이타를 시리얼로 출력하는 동시에 기록데이타를 데이타 변환회로에 공급하는 입출력회로(17)를 구비한 것을 특징으로 하는 반도체 기억장치.
  2. 제1항에 있어서, 상기 입출력 회로는 시프트 레지스터에 의하여 구성되어 있는 것을 특징으로 하는 반도체기억자치.
  3. 제1항에 있어서, 상기 메모리셀은 4치의 레벨에 의하여 2비트의 데이타를 기억하고, 상기 증폭회로군은 3종류의 레퍼런스 . 레벨이 설정된 3개의 센스 앰프에 의하여 구성되어 있는 것을 특징으로 하는 반도체 기억장치.
  4. 제1항에 있어서, 상기 메모리 셀은 4치의 레벨에 의하여 2비트의 데이타를 기억하고, 상기 증폭회로군은 3종류의 레퍼렌스. 레벨이 설정된 3개의 샘스 앰프에 의하여 구성되고, 각 센스 앰프의 프리챠지. 레벨은 전원전압을 3등분한 전원에 설정되어 있는 것을 특징으로 하는 반도체 기억장치.
  5. 제1항에 있어서, 상기 증폭회로군은 메모리셀의 데이타를 독출하는 동시에 상기 데이타 변환회로의 지시에 따라 독출한 데이타를 대응하는 메모리셀에 제기록하는 구성으로 되어있는 것을 특징으로 하는 반도체 기억장치.
  6. 제1항에 있어서, 상기 메모리셀 어레이는 정류의 데이타를 기억하는 제1의 셀(11) 및 착오검출용의 기억하는 제1의 셀(11) 및 착오검출용의 검사데이타를 기억하는 제2의 셀(12)에 의하여 구성되어 있는 것을 특징으로 하는 반도체 기억장치.
  7. 제6항에 있어서, 상기 검사데이타는 정규의 데이타 보다 적은 다치의 데이타에 의하여 구성되어 있는 것을 특징으로 하는 반도체기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910021470A 1990-11-28 1991-11-28 반도체 기억장치 KR950002290B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP90-328463 1990-11-28
JP2328463A JP2573416B2 (ja) 1990-11-28 1990-11-28 半導体記憶装置

Publications (2)

Publication Number Publication Date
KR920010617A true KR920010617A (ko) 1992-06-26
KR950002290B1 KR950002290B1 (ko) 1995-03-16

Family

ID=18210551

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910021470A KR950002290B1 (ko) 1990-11-28 1991-11-28 반도체 기억장치

Country Status (3)

Country Link
US (1) US5351210A (ko)
JP (1) JP2573416B2 (ko)
KR (1) KR950002290B1 (ko)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100299872B1 (ko) * 1998-06-29 2001-10-27 박종섭 다비트데이터기록제어회로
KR20030003312A (ko) * 2001-06-30 2003-01-10 주식회사 하이닉스반도체 다중 비트 커패시터를 갖는 반도체 메모리
KR100470378B1 (ko) * 1995-08-02 2005-06-21 산요덴키가부시키가이샤 신호기록장치,신호판독장치및신호기록·판독장치

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5218569A (en) 1991-02-08 1993-06-08 Banks Gerald J Electrically alterable non-volatile memory with n-bits per memory cell
US6002614A (en) 1991-02-08 1999-12-14 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
FR2705821B1 (fr) * 1993-05-24 1995-08-11 Sgs Thomson Microelectronics Mémoire dynamique.
EP0663666B1 (de) * 1994-01-12 1999-03-03 Siemens Aktiengesellschaft Integrierte Halbleiterspeicherschaltung und Verfahren zu ihrem Betrieb
US5440505A (en) * 1994-01-21 1995-08-08 Intel Corporation Method and circuitry for storing discrete amounts of charge in a single memory element
US5539690A (en) * 1994-06-02 1996-07-23 Intel Corporation Write verify schemes for flash memory with multilevel cells
US5485422A (en) * 1994-06-02 1996-01-16 Intel Corporation Drain bias multiplexing for multiple bit flash cell
US5515317A (en) * 1994-06-02 1996-05-07 Intel Corporation Addressing modes for a dynamic single bit per cell to multiple bit per cell memory
AU2593595A (en) * 1994-06-02 1996-01-04 Intel Corporation Sensing schemes for flash memory with multilevel cells
US5450363A (en) * 1994-06-02 1995-09-12 Intel Corporation Gray coding for a multilevel cell memory system
US5497354A (en) 1994-06-02 1996-03-05 Intel Corporation Bit map addressing schemes for flash memory
EP0763241B1 (en) * 1994-06-02 2001-10-17 Intel Corporation Dynamic single to multiple bit per cell memory
JPH08180688A (ja) * 1994-12-26 1996-07-12 Nec Corp 半導体記憶装置
US6353554B1 (en) 1995-02-27 2002-03-05 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US5815434A (en) * 1995-09-29 1998-09-29 Intel Corporation Multiple writes per a single erase for a nonvolatile memory
US5761110A (en) * 1996-12-23 1998-06-02 Lsi Logic Corporation Memory cell capable of storing more than two logic states by using programmable resistances
US5847990A (en) * 1996-12-23 1998-12-08 Lsi Logic Corporation Ram cell capable of storing 3 logic states
US5771187A (en) * 1996-12-23 1998-06-23 Lsi Logic Corporation Multiple level storage DRAM cell
US5808932A (en) * 1996-12-23 1998-09-15 Lsi Logic Corporation Memory system which enables storage and retrieval of more than two states in a memory cell
US5784328A (en) * 1996-12-23 1998-07-21 Lsi Logic Corporation Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array
US5982659A (en) * 1996-12-23 1999-11-09 Lsi Logic Corporation Memory cell capable of storing more than two logic states by using different via resistances
US5761114A (en) * 1997-02-19 1998-06-02 International Business Machines Corporation Multi-level storage gain cell with stepline
AUPO799197A0 (en) * 1997-07-15 1997-08-07 Silverbrook Research Pty Ltd Image processing method and apparatus (ART01)
US5915167A (en) * 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
US6360346B1 (en) * 1997-08-27 2002-03-19 Sony Corporation Storage unit, method of checking storage unit, reading and writing method
US5956350A (en) * 1997-10-27 1999-09-21 Lsi Logic Corporation Built in self repair for DRAMs using on-chip temperature sensing and heating
US5909404A (en) * 1998-03-27 1999-06-01 Lsi Logic Corporation Refresh sampling built-in self test and repair circuit
US6137739A (en) * 1998-06-29 2000-10-24 Hyundai Electronics Industries Co., Ltd. Multilevel sensing circuit and method thereof
US6816968B1 (en) * 1998-07-10 2004-11-09 Silverbrook Research Pty Ltd Consumable authentication protocol and system
US7660941B2 (en) * 2003-09-10 2010-02-09 Super Talent Electronics, Inc. Two-level RAM lookup table for block and page allocation and wear-leveling in limited-write flash-memories
US7333364B2 (en) * 2000-01-06 2008-02-19 Super Talent Electronics, Inc. Cell-downgrading and reference-voltage adjustment for a multi-bit-cell flash memory
US20050174841A1 (en) * 2004-02-05 2005-08-11 Iota Technology, Inc. Electronic memory with tri-level cell pair
US7352619B2 (en) 2004-02-05 2008-04-01 Iota Technology, Inc. Electronic memory with binary storage elements
JP4647446B2 (ja) * 2005-09-20 2011-03-09 富士通株式会社 半導体記憶装置
JP5052070B2 (ja) 2006-08-23 2012-10-17 ルネサスエレクトロニクス株式会社 データ読み出し回路及びデータ読み出し方法
US20080205120A1 (en) * 2007-02-23 2008-08-28 Chih-Ta Star Sung Multiple layer random accessing memory
US7966547B2 (en) * 2007-07-02 2011-06-21 International Business Machines Corporation Multi-bit error correction scheme in multi-level memory storage system
US7974124B2 (en) * 2009-06-24 2011-07-05 Sandisk Corporation Pointer based column selection techniques in non-volatile memories
WO2012053374A1 (en) * 2010-10-20 2012-04-26 Semiconductor Energy Laboratory Co., Ltd. Method for driving semiconductor device
KR20160074826A (ko) 2014-12-18 2016-06-29 삼성전자주식회사 반도체 장치

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0148488B1 (en) * 1983-12-23 1992-03-18 Hitachi, Ltd. Semiconductor memory having multiple level storage structure
US4649516A (en) * 1984-06-01 1987-03-10 International Business Machines Corp. Dynamic row buffer circuit for DRAM
JPS6163996A (ja) * 1984-09-05 1986-04-02 Nippon Telegr & Teleph Corp <Ntt> 情報記憶装置
KR900002664B1 (ko) * 1985-08-16 1990-04-21 가부시끼가이샤 히다찌세이사꾸쇼 시리얼 데이터 기억 반도체 메모리
JPH07114074B2 (ja) * 1985-12-18 1995-12-06 株式会社日立製作所 半導体記憶装置
JPS63149900A (ja) * 1986-12-15 1988-06-22 Toshiba Corp 半導体メモリ
JPS63273300A (ja) * 1987-04-30 1988-11-10 Nec Corp 半導体メモリ装置
US4888630A (en) * 1988-03-21 1989-12-19 Texas Instruments Incorporated Floating-gate transistor with a non-linear intergate dielectric
US4890259A (en) * 1988-07-13 1989-12-26 Information Storage Devices High density integrated circuit analog signal recording and playback system
JPH03162800A (ja) * 1989-08-29 1991-07-12 Mitsubishi Electric Corp 半導体メモリ装置
JP2790495B2 (ja) * 1989-11-02 1998-08-27 沖電気工業株式会社 不揮発性半導体記憶装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100470378B1 (ko) * 1995-08-02 2005-06-21 산요덴키가부시키가이샤 신호기록장치,신호판독장치및신호기록·판독장치
KR100299872B1 (ko) * 1998-06-29 2001-10-27 박종섭 다비트데이터기록제어회로
KR20030003312A (ko) * 2001-06-30 2003-01-10 주식회사 하이닉스반도체 다중 비트 커패시터를 갖는 반도체 메모리

Also Published As

Publication number Publication date
JPH04195995A (ja) 1992-07-15
US5351210A (en) 1994-09-27
JP2573416B2 (ja) 1997-01-22
KR950002290B1 (ko) 1995-03-16

Similar Documents

Publication Publication Date Title
KR920010617A (ko) 반도체 기억장치
KR920013446A (ko) 블럭라이트 기능을 구비하는 반도체기억장치
KR920013472A (ko) 반도체 기억장치
KR920010639A (ko) 강유전성 메모리용 감지증폭기 및 그 감지방법
DE69421429T2 (de) Halbleiterspeicher mit eingebautem parallelen Bitprüfmodus
KR940004820A (ko) 반도체 메모리 장치
KR880014572A (ko) 독출 데이타의 에러 검사 및 교정 기능을 갖는 반도체 메모리 장치
KR930001216A (ko) 랜덤 액세스 메모리 장치와 그 제어방법
KR870009392A (ko) 반도체 기억장치
KR930011242A (ko) 스태틱형 메모리
KR960008849A (ko) 반도체 기억장치
DE69220256T2 (de) Halbleiterspeicheranordnung
KR970063252A (ko) 다층 메모리 셀 어레이를 갖는 반도체 메모리 장치
KR920017115A (ko) 반도체기억장치
KR910013285A (ko) 불휘발성 반도체메모리
KR920010624A (ko) 반도체기억장치
KR850007159A (ko) 비트 에러 검출기능을 갖는 반도체 메모리장치
KR920020499A (ko) 반도체 기억 장치
KR960025777A (ko) 프리챠지 회로를 갖는 반도체 메모리 디바이스
KR920003314A (ko) 반도체 메모리장치
KR910020450A (ko) 반도체기억장치를 위한 테스트장치
KR960029806A (ko) 반도체 메모리
KR920018752A (ko) 반도체 기억장치
KR960018902A (ko) 동기식 메모리장치
KR900010778A (ko) 반도체 메모리장치

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080227

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee