DE69130210D1 - Halbleiterspeicher mit hochgeschwindigkeitsadressendekodierer - Google Patents

Halbleiterspeicher mit hochgeschwindigkeitsadressendekodierer

Info

Publication number
DE69130210D1
DE69130210D1 DE69130210T DE69130210T DE69130210D1 DE 69130210 D1 DE69130210 D1 DE 69130210D1 DE 69130210 T DE69130210 T DE 69130210T DE 69130210 T DE69130210 T DE 69130210T DE 69130210 D1 DE69130210 D1 DE 69130210D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
address decoder
speed address
speed
decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69130210T
Other languages
English (en)
Other versions
DE69130210T2 (de
Inventor
Satoru Kawamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Publication of DE69130210D1 publication Critical patent/DE69130210D1/de
Application granted granted Critical
Publication of DE69130210T2 publication Critical patent/DE69130210T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408Address circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE69130210T 1990-11-16 1991-11-15 Halbleiterspeicher mit hochgeschwindigkeitsadressendekodierer Expired - Lifetime DE69130210T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP31056690 1990-11-16
PCT/JP1991/001563 WO1992009084A1 (en) 1990-11-16 1991-11-15 Semiconductor memory having high-speed address decoder

Publications (2)

Publication Number Publication Date
DE69130210D1 true DE69130210D1 (de) 1998-10-22
DE69130210T2 DE69130210T2 (de) 1999-01-21

Family

ID=18006786

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130210T Expired - Lifetime DE69130210T2 (de) 1990-11-16 1991-11-15 Halbleiterspeicher mit hochgeschwindigkeitsadressendekodierer

Country Status (5)

Country Link
US (1) US5394373A (de)
EP (1) EP0511397B1 (de)
KR (1) KR970004746B1 (de)
DE (1) DE69130210T2 (de)
WO (1) WO1992009084A1 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05234371A (ja) * 1992-02-21 1993-09-10 Fujitsu Ltd ダイナミックram
JPH07169276A (ja) * 1993-12-13 1995-07-04 Toshiba Corp 同期型メモリ
JP3226426B2 (ja) * 1994-09-27 2001-11-05 松下電器産業株式会社 半導体メモリ及びその使用方法並びに画像プロセッサ
US5526320A (en) * 1994-12-23 1996-06-11 Micron Technology Inc. Burst EDO memory device
US5717654A (en) * 1995-02-10 1998-02-10 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing
US5546353A (en) * 1995-05-26 1996-08-13 National Semiconductor Corporation Partitioned decode circuit for low power operation
DE69532376T2 (de) * 1995-05-31 2004-06-09 United Memories, Inc., Colorado Springs Schaltung und Verfahren zum Zugriff auf Speicherzellen einer Speicheranordnung
US5822252A (en) * 1996-03-29 1998-10-13 Aplus Integrated Circuits, Inc. Flash memory wordline decoder with overerase repair
US5687121A (en) * 1996-03-29 1997-11-11 Aplus Integrated Circuits, Inc. Flash EEPROM worldline decoder
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
JP3827406B2 (ja) * 1997-06-25 2006-09-27 富士通株式会社 クロック同期型入力回路及びそれを利用した半導体記憶装置
US5923604A (en) * 1997-12-23 1999-07-13 Micron Technology, Inc. Method and apparatus for anticipatory selection of external or internal addresses in a synchronous memory device
JP3204450B2 (ja) * 1998-04-15 2001-09-04 日本電気株式会社 アドレスデコード回路及びアドレスデコード方法
US6072746A (en) * 1998-08-14 2000-06-06 International Business Machines Corporation Self-timed address decoder for register file and compare circuit of a multi-port CAM
US6144611A (en) * 1999-09-07 2000-11-07 Motorola Inc. Method for clearing memory contents and memory array capable of performing the same
US6185148B1 (en) * 2000-02-21 2001-02-06 Hewlett-Packard Company General purpose decode implementation for multiported memory array circuits
JP3376998B2 (ja) * 2000-03-08 2003-02-17 日本電気株式会社 半導体記憶装置
JP3948933B2 (ja) * 2001-11-07 2007-07-25 富士通株式会社 半導体記憶装置、及びその制御方法
US6798711B2 (en) * 2002-03-19 2004-09-28 Micron Technology, Inc. Memory with address management
US7385858B2 (en) * 2005-11-30 2008-06-10 Mosaid Technologies Incorporated Semiconductor integrated circuit having low power consumption with self-refresh
JP2007293933A (ja) * 2006-04-21 2007-11-08 Matsushita Electric Ind Co Ltd 半導体記憶装置
JP4984759B2 (ja) * 2006-09-05 2012-07-25 富士通セミコンダクター株式会社 半導体記憶装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5381021A (en) * 1976-12-27 1978-07-18 Nippon Telegr & Teleph Corp <Ntt> Address input circuit
JPS5381020A (en) * 1976-12-27 1978-07-18 Fujitsu Ltd Error check method for memory unit
US4207618A (en) * 1978-06-26 1980-06-10 Texas Instruments Incorporated On-chip refresh for dynamic memory
JPS55150192A (en) * 1979-05-08 1980-11-21 Nec Corp Memory unit
JPS55150191A (en) * 1979-05-08 1980-11-21 Nec Corp Information refreshing method of semiconductor integrated circuit
DE3232215A1 (de) * 1982-08-30 1984-03-01 Siemens AG, 1000 Berlin und 8000 München Monolithisch integrierte digitale halbleiterschaltung
JPS59157891A (ja) * 1983-02-25 1984-09-07 Toshiba Corp メモリ装置におけるメモリセル選択回路
JPS60167194A (ja) * 1984-02-09 1985-08-30 Fujitsu Ltd 半導体記憶装置
JPS6117292A (ja) * 1984-07-04 1986-01-25 Hitachi Ltd 半導体記憶装置
JPS6142795A (ja) * 1984-08-03 1986-03-01 Toshiba Corp 半導体記憶装置の行デコ−ダ系
JPS61126687A (ja) * 1984-11-22 1986-06-14 Hitachi Ltd ダイナミツク型ram
JPS6117291A (ja) * 1985-06-21 1986-01-25 Hitachi Ltd メモリの駆動方式
JPH01205788A (ja) * 1988-02-12 1989-08-18 Toshiba Corp 半導体集積回路
JPH0221490A (ja) * 1988-07-07 1990-01-24 Oki Electric Ind Co Ltd ダイナミック・ランダム・アクセス・メモリ
JPH0713862B2 (ja) * 1988-08-31 1995-02-15 三菱電機株式会社 半導体記憶装置
JPH02141993A (ja) * 1988-11-21 1990-05-31 Toshiba Corp 半導体記憶装置
JPH02247892A (ja) * 1989-03-20 1990-10-03 Fujitsu Ltd ダイナミックランダムアクセスメモリ

Also Published As

Publication number Publication date
EP0511397A4 (en) 1994-07-06
WO1992009084A1 (en) 1992-05-29
KR970004746B1 (ko) 1997-04-03
DE69130210T2 (de) 1999-01-21
EP0511397B1 (de) 1998-09-16
EP0511397A1 (de) 1992-11-04
US5394373A (en) 1995-02-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU VLSI LTD., KASUGAI, AICHI, JP

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

Owner name: FUJITSU VLSI LTD., KASUGAI, AICHI, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE