JPS55150191A - Information refreshing method of semiconductor integrated circuit - Google Patents
Information refreshing method of semiconductor integrated circuitInfo
- Publication number
- JPS55150191A JPS55150191A JP5614779A JP5614779A JPS55150191A JP S55150191 A JPS55150191 A JP S55150191A JP 5614779 A JP5614779 A JP 5614779A JP 5614779 A JP5614779 A JP 5614779A JP S55150191 A JPS55150191 A JP S55150191A
- Authority
- JP
- Japan
- Prior art keywords
- refreshing
- potential
- refresh
- signal
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To lessen an unusable time of a dynamic memory, etc., by constantly monitoring a reference cell formed on the same semiconductor substrate and by refreshing when its refresh signal and a refresh enable signal from a semiconductor integrated circuit are both generated at a time. CONSTITUTION:A reference element is represented by capacitor C and its information holding state is decided by a potential at node 1. A potential at node 2 is a refresh request signal. After refreshing, transistors T1 and T2 are OFF and ON respectively and potentials at nodes 1 and 2 are Vs and low respectively. Even when a semiconductor integrated circuit is placed in a refresh enable state, transistor T6 is OFF and terminal R is held at a high potential. When node 1 decreases in potential as time passes, T2 turns OFF to turn T6 ON and once a refresh signal holding terminal T arrives at a high potential, refreshing comes into effect. Simultaneously, a signal is sent to terminal G and the reference element is also refreshed. Therefore, the unusable time due to refreshing is lessened.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5614779A JPS55150191A (en) | 1979-05-08 | 1979-05-08 | Information refreshing method of semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5614779A JPS55150191A (en) | 1979-05-08 | 1979-05-08 | Information refreshing method of semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55150191A true JPS55150191A (en) | 1980-11-21 |
Family
ID=13018964
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5614779A Pending JPS55150191A (en) | 1979-05-08 | 1979-05-08 | Information refreshing method of semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55150191A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6132299A (en) * | 1984-07-24 | 1986-02-14 | Seiko Epson Corp | Semiconductor memory |
US4982369A (en) * | 1986-11-07 | 1991-01-01 | Fujitsu Limited | Self-refresh semiconductor memory device responsive to a refresh request signal |
US5392251A (en) * | 1993-07-13 | 1995-02-21 | Micron Semiconductor, Inc. | Controlling dynamic memory refresh cycle time |
US5394373A (en) * | 1990-11-16 | 1995-02-28 | Fujitsu Limited | Semiconductor memory having a high-speed address decoder |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5365631A (en) * | 1976-11-24 | 1978-06-12 | Fujitsu Ltd | Data processor |
JPS5391638A (en) * | 1977-01-24 | 1978-08-11 | Nec Corp | Semiconductor temporal memory unit |
-
1979
- 1979-05-08 JP JP5614779A patent/JPS55150191A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5365631A (en) * | 1976-11-24 | 1978-06-12 | Fujitsu Ltd | Data processor |
JPS5391638A (en) * | 1977-01-24 | 1978-08-11 | Nec Corp | Semiconductor temporal memory unit |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6132299A (en) * | 1984-07-24 | 1986-02-14 | Seiko Epson Corp | Semiconductor memory |
US4982369A (en) * | 1986-11-07 | 1991-01-01 | Fujitsu Limited | Self-refresh semiconductor memory device responsive to a refresh request signal |
US5394373A (en) * | 1990-11-16 | 1995-02-28 | Fujitsu Limited | Semiconductor memory having a high-speed address decoder |
US5392251A (en) * | 1993-07-13 | 1995-02-21 | Micron Semiconductor, Inc. | Controlling dynamic memory refresh cycle time |
US5539703A (en) * | 1993-07-13 | 1996-07-23 | Micron Technology, Inc. | Dynamic memory device including apparatus for controlling refresh cycle time |
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