DE69130580D1 - Cache-Speicheranordnung - Google Patents

Cache-Speicheranordnung

Info

Publication number
DE69130580D1
DE69130580D1 DE69130580T DE69130580T DE69130580D1 DE 69130580 D1 DE69130580 D1 DE 69130580D1 DE 69130580 T DE69130580 T DE 69130580T DE 69130580 T DE69130580 T DE 69130580T DE 69130580 D1 DE69130580 D1 DE 69130580D1
Authority
DE
Germany
Prior art keywords
cache memory
memory arrangement
arrangement
cache
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69130580T
Other languages
English (en)
Other versions
DE69130580T2 (de
Inventor
Shigenori Shimizu
Moriyoshi Ohara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69130580D1 publication Critical patent/DE69130580D1/de
Publication of DE69130580T2 publication Critical patent/DE69130580T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69130580T 1990-01-16 1991-01-04 Cache-Speicheranordnung Expired - Fee Related DE69130580T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004668A JPH061463B2 (ja) 1990-01-16 1990-01-16 マルチプロセッサ・システムおよびそのプライベート・キャッシュ制御方法

Publications (2)

Publication Number Publication Date
DE69130580D1 true DE69130580D1 (de) 1999-01-21
DE69130580T2 DE69130580T2 (de) 1999-07-15

Family

ID=11590292

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130580T Expired - Fee Related DE69130580T2 (de) 1990-01-16 1991-01-04 Cache-Speicheranordnung

Country Status (4)

Country Link
US (1) US5228136A (de)
EP (1) EP0438211B1 (de)
JP (1) JPH061463B2 (de)
DE (1) DE69130580T2 (de)

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US5161219A (en) * 1989-01-13 1992-11-03 International Business Machines Corporation Computer system with input/output cache
US5404483A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
GB9118312D0 (en) * 1991-08-24 1991-10-09 Motorola Inc Real time cache implemented by dual purpose on-chip memory
US5627967A (en) * 1991-09-24 1997-05-06 International Business Machines Corporation Automated generation on file access control system commands in a data processing system with front end processing of a master list
WO1993020505A2 (en) 1992-03-31 1993-10-14 Seiko Epson Corporation Superscalar risc instruction scheduling
US5553266A (en) * 1992-04-24 1996-09-03 Digital Equipment Corporation Update vs. invalidate policy for a snoopy bus protocol
DE69323790T2 (de) * 1992-04-29 1999-10-07 Sun Microsystems, Inc. Verfahren und Vorrichtung für mehreren ausstehende Operationen in einem cachespeicherkohärenten Multiprozessorsystem
JP3637920B2 (ja) 1992-05-01 2005-04-13 セイコーエプソン株式会社 スーパースケーラマイクロプロセサに於て命令をリタイアさせるシステム及び方法
US5511226A (en) * 1992-08-25 1996-04-23 Intel Corporation System for generating snoop addresses and conditionally generating source addresses whenever there is no snoop hit, the source addresses lagging behind the corresponding snoop addresses
WO1994016384A1 (en) 1992-12-31 1994-07-21 Seiko Epson Corporation System and method for register renaming
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US5664153A (en) * 1993-04-21 1997-09-02 Intel Corporation Page open/close scheme based on high order address bit and likelihood of page access
FR2707774B1 (fr) * 1993-07-15 1995-08-18 Bull Sa Procédé de gestion cohérente des échanges entre des niveaux d'une hiérarchie de mémoires à au moins trois niveaux.
FR2707777B1 (fr) * 1993-07-15 1995-08-18 Bull Sa Ensemble informatique à mémoire partagée.
FR2707778B1 (fr) * 1993-07-15 1995-08-18 Bull Sa NÓoeud de processeurs.
FR2707776B1 (fr) 1993-07-15 1995-08-18 Bull Sa Procédé de gestion de mémoires d'un système informatique, système informatique mémoire et support d'enregistrement mettant en Óoeuvre le procédé.
US5630095A (en) * 1993-08-03 1997-05-13 Motorola Inc. Method for use with a data coherency protocol allowing multiple snoop queries to a single snoop transaction and system therefor
US5581793A (en) * 1993-08-24 1996-12-03 Micron Electronics, Inc. System for bypassing setup states in a bus operation
US5655102A (en) * 1993-09-29 1997-08-05 Silicon Graphics, Inc. System and method for piggybacking of read responses on a shared memory multiprocessor bus
US5535352A (en) * 1994-03-24 1996-07-09 Hewlett-Packard Company Access hints for input/output address translation mechanisms
US5651134A (en) * 1994-10-26 1997-07-22 Ncr Corporation Method for configuring a cache memory to store only data, only code, or code and data based on the operating characteristics of the application program
US5530932A (en) * 1994-12-23 1996-06-25 Intel Corporation Cache coherent multiprocessing computer system with reduced power operating features
US5787476A (en) * 1995-05-05 1998-07-28 Silicon Graphics, Inc. System and method for maintaining coherency of virtual-to-physical memory translations in a multiprocessor computer
US6106565A (en) * 1997-02-27 2000-08-22 Advanced Micro Devices, Inc. System and method for hardware emulation of a digital circuit
US5923898A (en) * 1997-05-14 1999-07-13 International Business Machines Corporation System for executing I/O request when an I/O request queue entry matches a snoop table entry or executing snoop when not matched
US6023747A (en) * 1997-12-17 2000-02-08 International Business Machines Corporation Method and system for handling conflicts between cache operation requests in a data processing system
US6128706A (en) * 1998-02-03 2000-10-03 Institute For The Development Of Emerging Architectures, L.L.C. Apparatus and method for a load bias--load with intent to semaphore
US6272603B1 (en) 1998-02-17 2001-08-07 International Business Machines Corporation Cache coherency protocol having hovering (H), recent (R), and tagged (T) states
US6415358B1 (en) 1998-02-17 2002-07-02 International Business Machines Corporation Cache coherency protocol having an imprecise hovering (H) state for instructions and data
US6292872B1 (en) 1998-02-17 2001-09-18 International Business Machines Corporation Cache coherency protocol having hovering (H) and recent (R) states
US6263407B1 (en) 1998-02-17 2001-07-17 International Business Machines Corporation Cache coherency protocol including a hovering (H) state having a precise mode and an imprecise mode
US6253285B1 (en) 1998-04-16 2001-06-26 Compaq Computer Corporation Method and apparatus for minimizing dcache index match aliasing using hashing in synonym/subset processing
US6370622B1 (en) 1998-11-20 2002-04-09 Massachusetts Institute Of Technology Method and apparatus for curious and column caching
US6651088B1 (en) * 1999-07-20 2003-11-18 Hewlett-Packard Development Company, L.P. Method for reducing coherent misses in shared-memory multiprocessors utilizing lock-binding prefetchs
US6484238B1 (en) 1999-12-20 2002-11-19 Hewlett-Packard Company Apparatus and method for detecting snoop hits on victim lines issued to a higher level cache
US6631474B1 (en) * 1999-12-31 2003-10-07 Intel Corporation System to coordinate switching between first and second processors and to coordinate cache coherency between first and second processors during switching
JP2002032265A (ja) * 2000-07-14 2002-01-31 Hitachi Ltd キャッシュ・アクセス制御方式およびデータ処理システム
US7664823B1 (en) * 2003-09-24 2010-02-16 Cisco Technology, Inc. Partitioned packet processing in a multiprocessor environment
JP4912790B2 (ja) * 2006-08-18 2012-04-11 富士通株式会社 システムコントローラ，スヌープタグ更新方法および情報処理装置
CN104951240B (zh) 2014-03-26 2018-08-24 阿里巴巴集团控股有限公司 一种数据处理方法及处理器

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US3848234A (en) * 1973-04-04 1974-11-12 Sperry Rand Corp Multi-processor system with multiple cache memories
US3840862A (en) * 1973-09-27 1974-10-08 Honeywell Inf Systems Status indicator apparatus for tag directory in associative stores
US3938097A (en) * 1974-04-01 1976-02-10 Xerox Corporation Memory and buffer arrangement for digital computers
US4392200A (en) * 1980-01-28 1983-07-05 Digital Equipment Corporation Cached multiprocessor system with pipeline timing
US4843542A (en) * 1986-11-12 1989-06-27 Xerox Corporation Virtual memory cache for use in multi-processing systems
JPH0668735B2 (ja) * 1987-02-09 1994-08-31 日本電気アイシーマイコンシステム株式会社 キヤツシユメモリ−
US4959777A (en) * 1987-07-27 1990-09-25 Motorola Computer X Write-shared cache circuit for multiprocessor system
GB8728494D0 (en) * 1987-12-05 1988-01-13 Int Computers Ltd Multi-cache data storage system
EP0343567A3 (de) * 1988-05-25 1991-01-09 Hitachi, Ltd. Mehrprozessoranordnung und Cache-Speichervorrichtung zur Verwendung in dieser Anordnung
US5025365A (en) * 1988-11-14 1991-06-18 Unisys Corporation Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors

Also Published As

Publication number Publication date
EP0438211A3 (en) 1992-08-05
DE69130580T2 (de) 1999-07-15
JPH03217963A (ja) 1991-09-25
EP0438211B1 (de) 1998-12-09
JPH061463B2 (ja) 1994-01-05
US5228136A (en) 1993-07-13
EP0438211A2 (de) 1991-07-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee