DE69127582T2 - Verfahren zur Herstellung eines Halbleitersubstrates und Verfahren zur Herstellung einer Halbleiteranordnung unter Verwendung dieses Substrates - Google Patents

Verfahren zur Herstellung eines Halbleitersubstrates und Verfahren zur Herstellung einer Halbleiteranordnung unter Verwendung dieses Substrates

Info

Publication number
DE69127582T2
DE69127582T2 DE69127582T DE69127582T DE69127582T2 DE 69127582 T2 DE69127582 T2 DE 69127582T2 DE 69127582 T DE69127582 T DE 69127582T DE 69127582 T DE69127582 T DE 69127582T DE 69127582 T2 DE69127582 T2 DE 69127582T2
Authority
DE
Germany
Prior art keywords
producing
semiconductor substrate
substrate according
wafer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69127582T
Other languages
German (de)
English (en)
Other versions
DE69127582D1 (de
Inventor
Sadahiro Kishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69127582D1 publication Critical patent/DE69127582D1/de
Publication of DE69127582T2 publication Critical patent/DE69127582T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12—Preparing bulk and homogeneous wafers
    • H10P90/123—Preparing bulk and homogeneous wafers by grinding or lapping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12—Preparing bulk and homogeneous wafers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/402—Chemomechanical polishing [CMP] of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/02—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by rotary tools, e.g. drills
    • B28D5/022—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by rotary tools, e.g. drills by cutting with discs or wheels

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE69127582T 1990-05-18 1991-05-16 Verfahren zur Herstellung eines Halbleitersubstrates und Verfahren zur Herstellung einer Halbleiteranordnung unter Verwendung dieses Substrates Expired - Fee Related DE69127582T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP12972590 1990-05-18
JP23777590 1990-09-07

Publications (2)

Publication Number Publication Date
DE69127582D1 DE69127582D1 (de) 1997-10-16
DE69127582T2 true DE69127582T2 (de) 1998-03-26

Family

ID=26465027

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69127582T Expired - Fee Related DE69127582T2 (de) 1990-05-18 1991-05-16 Verfahren zur Herstellung eines Halbleitersubstrates und Verfahren zur Herstellung einer Halbleiteranordnung unter Verwendung dieses Substrates

Country Status (4)

Country Link
US (1) US5227339A (enExample)
EP (1) EP0460437B1 (enExample)
KR (1) KR950003227B1 (enExample)
DE (1) DE69127582T2 (enExample)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06112451A (ja) * 1992-09-29 1994-04-22 Nagano Denshi Kogyo Kk Ｓｏｉ基板の製造方法
US5427644A (en) * 1993-01-11 1995-06-27 Tokyo Seimitsu Co., Ltd. Method of manufacturing semiconductor wafer and system therefor
US5360509A (en) * 1993-03-08 1994-11-01 Gi Corporation Low cost method of fabricating epitaxial semiconductor devices
US5389579A (en) * 1993-04-05 1995-02-14 Motorola, Inc. Method for single sided polishing of a semiconductor wafer
EP0709878B1 (en) * 1994-10-24 1998-04-01 Naoetsu Electronics Company Method for the preparation of discrete substrate plates of semiconductor silicon wafer
JP2910507B2 (ja) * 1993-06-08 1999-06-23 信越半導体株式会社 半導体ウエーハの製造方法
US5733175A (en) 1994-04-25 1998-03-31 Leach; Michael A. Polishing a workpiece using equal velocity at all points overlapping a polisher
US5607341A (en) 1994-08-08 1997-03-04 Leach; Michael A. Method and structure for polishing a wafer during manufacture of integrated circuits
JPH08222798A (ja) * 1995-02-15 1996-08-30 Mitsubishi Electric Corp 半導体レーザの製造方法
US5937312A (en) * 1995-03-23 1999-08-10 Sibond L.L.C. Single-etch stop process for the manufacture of silicon-on-insulator wafers
US5635414A (en) * 1995-03-28 1997-06-03 Zakaluk; Gregory Low cost method of fabricating shallow junction, Schottky semiconductor devices
US6054372A (en) * 1995-04-03 2000-04-25 Aptek Industries, Inc. Stress-free silicon wafer and a die or chip made therefrom
US6268237B1 (en) 1995-04-03 2001-07-31 Aptek Industries, Inc. Stress-free silicon wafer and a die or chip made therefrom and method
US5733814A (en) * 1995-04-03 1998-03-31 Aptek Industries, Inc. Flexible electronic card and method
JP3213563B2 (ja) * 1997-03-11 2001-10-02 株式会社スーパーシリコン研究所 ノッチレスウェーハの製造方法
US6391744B1 (en) * 1997-03-19 2002-05-21 The United States Of America As Represented By The National Security Agency Method of fabricating a non-SOI device on an SOI starting wafer and thinning the same
WO1999009588A1 (en) * 1997-08-21 1999-02-25 Memc Electronic Materials, Inc. Method of processing semiconductor wafers
US6273791B1 (en) * 1997-11-18 2001-08-14 Mitsui Chemicals, Inc. Method of producing semiconductor wafer
WO1999031723A1 (en) * 1997-12-12 1999-06-24 Memc Electronic Materials, Inc. Method of improving the flatness of polished semiconductor wafers
US6248651B1 (en) 1998-06-24 2001-06-19 General Semiconductor, Inc. Low cost method of fabricating transient voltage suppressor semiconductor devices or the like
JP3329288B2 (ja) * 1998-11-26 2002-09-30 信越半導体株式会社 半導体ウエーハおよびその製造方法
US6214704B1 (en) 1998-12-16 2001-04-10 Memc Electronic Materials, Inc. Method of processing semiconductor wafers to build in back surface damage
EP1134808B1 (en) * 1999-07-15 2011-10-05 Shin-Etsu Handotai Co., Ltd. A method of producing a bonded wafer
FR2797714B1 (fr) * 1999-08-20 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
US6383056B1 (en) 1999-12-02 2002-05-07 Yin Ming Wang Plane constructed shaft system used in precision polishing and polishing apparatuses
FR2819099B1 (fr) 2000-12-28 2003-09-26 Commissariat Energie Atomique Procede de realisation d'une structure empilee
JP2002334927A (ja) * 2001-05-11 2002-11-22 Hitachi Ltd 半導体装置の製造方法
FR2835652B1 (fr) * 2002-02-04 2005-04-15 St Microelectronics Sa Procede de fabrication d'un circuit integre comportant des transistors bipolaires, en particulier a heterojonction si/sige, et des transistors a effet de champ a grilles isolees, et circuit integre correspondant
JP2004022899A (ja) * 2002-06-18 2004-01-22 Shinko Electric Ind Co Ltd 薄シリコンウエーハの加工方法
JP2004119943A (ja) * 2002-09-30 2004-04-15 Renesas Technology Corp 半導体ウェハおよびその製造方法
DE102005046726B4 (de) * 2005-09-29 2012-02-02 Siltronic Ag Nichtpolierte monokristalline Siliziumscheibe und Verfahren zu ihrer Herstellung
JP4533934B2 (ja) 2008-01-15 2010-09-01 エプソントヨコム株式会社 振動片及び振動子の製造方法
US9882007B2 (en) * 2012-07-03 2018-01-30 Rfhic Corporation Handle for semiconductor-on-diamond wafers and method of manufacture
FI129826B (en) * 2020-10-08 2022-09-15 Okmetic Oy Manufacture method of a high-resistivity silicon handle wafer for a hybrid substrate structure

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0161740B1 (en) * 1984-05-09 1991-06-12 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor substrate
JPS62154614A (ja) * 1985-12-27 1987-07-09 Toshiba Corp 接合型半導体基板の製造方法
JPH06103678B2 (ja) * 1987-11-28 1994-12-14 株式会社東芝 半導体基板の加工方法
US5051378A (en) * 1988-11-09 1991-09-24 Sony Corporation Method of thinning a semiconductor wafer
JP2825322B2 (ja) * 1989-09-13 1998-11-18 株式会社東芝 誘電体分離構造を有する半導体基板の製造方法

Also Published As

Publication number Publication date
KR950003227B1 (ko) 1995-04-06
KR910020806A (ko) 1991-12-20
DE69127582D1 (de) 1997-10-16
EP0460437A3 (enExample) 1995-04-19
US5227339A (en) 1993-07-13
EP0460437A2 (en) 1991-12-11
EP0460437B1 (en) 1997-09-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee