DE69126463T2 - Verfahren zur Herstellung eines leitenden Elements - Google Patents

Verfahren zur Herstellung eines leitenden Elements

Info

Publication number
DE69126463T2
DE69126463T2 DE69126463T DE69126463T DE69126463T2 DE 69126463 T2 DE69126463 T2 DE 69126463T2 DE 69126463 T DE69126463 T DE 69126463T DE 69126463 T DE69126463 T DE 69126463T DE 69126463 T2 DE69126463 T2 DE 69126463T2
Authority
DE
Germany
Prior art keywords
producing
conductive element
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69126463T
Other languages
English (en)
Other versions
DE69126463D1 (de
Inventor
Yuu Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69126463D1 publication Critical patent/DE69126463D1/de
Application granted granted Critical
Publication of DE69126463T2 publication Critical patent/DE69126463T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H01L29/66871—Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69126463T 1990-03-20 1991-03-15 Verfahren zur Herstellung eines leitenden Elements Expired - Fee Related DE69126463T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2068022A JP2778600B2 (ja) 1990-03-20 1990-03-20 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69126463D1 DE69126463D1 (de) 1997-07-17
DE69126463T2 true DE69126463T2 (de) 1997-09-25

Family

ID=13361774

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69126463T Expired - Fee Related DE69126463T2 (de) 1990-03-20 1991-03-15 Verfahren zur Herstellung eines leitenden Elements

Country Status (5)

Country Link
US (1) US5264382A (de)
EP (1) EP0448307B1 (de)
JP (1) JP2778600B2 (de)
KR (1) KR930010053B1 (de)
DE (1) DE69126463T2 (de)

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JP2870485B2 (ja) * 1996-06-03 1999-03-17 日本電気株式会社 半導体装置の製造方法
US6010955A (en) * 1996-09-23 2000-01-04 Kabushiki Kaisha Toshiba Electrical connection forming process for semiconductor devices
US5912820A (en) * 1997-01-22 1999-06-15 Unisys Corporation Method and apparatus for distributing a clock tree within a hierarchical circuit design
US6346438B1 (en) * 1997-06-30 2002-02-12 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
US6297115B1 (en) 1998-11-06 2001-10-02 Advanced Micro Devices, Inc. Cmos processs with low thermal budget
US6225173B1 (en) 1998-11-06 2001-05-01 Advanced Micro Devices, Inc. Recessed channel structure for manufacturing shallow source/drain extensions
US5985726A (en) * 1998-11-06 1999-11-16 Advanced Micro Devices, Inc. Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET
US6200869B1 (en) 1998-11-06 2001-03-13 Advanced Micro Devices, Inc. Method of fabricating an integrated circuit with ultra-shallow source/drain extensions
US6265291B1 (en) 1999-01-04 2001-07-24 Advanced Micro Devices, Inc. Circuit fabrication method which optimizes source/drain contact resistance
US6225176B1 (en) 1999-02-22 2001-05-01 Advanced Micro Devices, Inc. Step drain and source junction formation
US6271095B1 (en) 1999-02-22 2001-08-07 Advanced Micro Devices, Inc. Locally confined deep pocket process for ULSI mosfets
US6184097B1 (en) 1999-02-22 2001-02-06 Advanced Micro Devices, Inc. Process for forming ultra-shallow source/drain extensions
US6291278B1 (en) 1999-05-03 2001-09-18 Advanced Micro Devices, Inc. Method of forming transistors with self aligned damascene gate contact
US6492249B2 (en) 1999-05-03 2002-12-10 Advanced Micro Devices, Inc. High-K gate dielectric process with process with self aligned damascene contact to damascene gate and a low-k inter level dielectric
US6271132B1 (en) 1999-05-03 2001-08-07 Advanced Micro Devices, Inc. Self-aligned source and drain extensions fabricated in a damascene contact and gate process
US6194748B1 (en) 1999-05-03 2001-02-27 Advanced Micro Devices, Inc. MOSFET with suppressed gate-edge fringing field effect
JP3762148B2 (ja) 1999-06-30 2006-04-05 株式会社東芝 半導体装置の製造方法
US6265293B1 (en) 1999-08-27 2001-07-24 Advanced Micro Devices, Inc. CMOS transistors fabricated in optimized RTA scheme
US6403433B1 (en) 1999-09-16 2002-06-11 Advanced Micro Devices, Inc. Source/drain doping technique for ultra-thin-body SOI MOS transistors
US6248637B1 (en) 1999-09-24 2001-06-19 Advanced Micro Devices, Inc. Process for manufacturing MOS Transistors having elevated source and drain regions
US6333244B1 (en) 2000-01-26 2001-12-25 Advanced Micro Devices, Inc. CMOS fabrication process with differential rapid thermal anneal scheme
US6372589B1 (en) 2000-04-19 2002-04-16 Advanced Micro Devices, Inc. Method of forming ultra-shallow source/drain extension by impurity diffusion from doped dielectric spacer
US6420218B1 (en) 2000-04-24 2002-07-16 Advanced Micro Devices, Inc. Ultra-thin-body SOI MOS transistors having recessed source and drain regions
US6368947B1 (en) 2000-06-20 2002-04-09 Advanced Micro Devices, Inc. Process utilizing a cap layer optimized to reduce gate line over-melt
US6361874B1 (en) 2000-06-20 2002-03-26 Advanced Micro Devices, Inc. Dual amorphization process optimized to reduce gate line over-melt
US6399450B1 (en) 2000-07-05 2002-06-04 Advanced Micro Devices, Inc. Low thermal budget process for manufacturing MOS transistors having elevated source and drain regions
US6630386B1 (en) 2000-07-18 2003-10-07 Advanced Micro Devices, Inc CMOS manufacturing process with self-amorphized source/drain junctions and extensions
US6521502B1 (en) 2000-08-07 2003-02-18 Advanced Micro Devices, Inc. Solid phase epitaxy activation process for source/drain junction extensions and halo regions
US6472282B1 (en) 2000-08-15 2002-10-29 Advanced Micro Devices, Inc. Self-amorphized regions for transistors
US6514809B1 (en) * 2000-11-03 2003-02-04 Advanced Micro Devices, Inc. SOI field effect transistors with body contacts formed by selective etch and fill
US6787424B1 (en) 2001-02-09 2004-09-07 Advanced Micro Devices, Inc. Fully depleted SOI transistor with elevated source and drain
US6551885B1 (en) 2001-02-09 2003-04-22 Advanced Micro Devices, Inc. Low temperature process for a thin film transistor
US6403434B1 (en) 2001-02-09 2002-06-11 Advanced Micro Devices, Inc. Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric
US6756277B1 (en) 2001-02-09 2004-06-29 Advanced Micro Devices, Inc. Replacement gate process for transistors having elevated source and drain regions
US6495437B1 (en) 2001-02-09 2002-12-17 Advanced Micro Devices, Inc. Low temperature process to locally form high-k gate dielectrics
US6509253B1 (en) 2001-02-16 2003-01-21 Advanced Micro Devices, Inc. T-shaped gate electrode for reduced resistance
US6420776B1 (en) 2001-03-01 2002-07-16 Amkor Technology, Inc. Structure including electronic components singulated using laser cutting
KR100469128B1 (ko) * 2002-11-07 2005-01-29 삼성전자주식회사 자기정렬된 얕은 트렌치 소자분리를 갖는 불휘발성 메모리장치의 플로팅 게이트 형성방법
US6905923B1 (en) 2003-07-15 2005-06-14 Advanced Micro Devices, Inc. Offset spacer process for forming N-type transistors
KR100487657B1 (ko) * 2003-08-13 2005-05-03 삼성전자주식회사 리세스된 게이트를 갖는 모스 트렌지스터 및 그의 제조방법
US7312125B1 (en) 2004-02-05 2007-12-25 Advanced Micro Devices, Inc. Fully depleted strained semiconductor on insulator transistor and method of making the same
US8357571B2 (en) * 2010-09-10 2013-01-22 Cree, Inc. Methods of forming semiconductor contacts
CN102655093B (zh) * 2011-03-02 2014-12-10 上海华虹宏力半导体制造有限公司 厚绝缘膜的工艺实现方法
US9461143B2 (en) 2012-09-19 2016-10-04 Intel Corporation Gate contact structure over active gate and method to fabricate same

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JPS5772384A (en) * 1980-10-24 1982-05-06 Nippon Telegr & Teleph Corp <Ntt> Manufacture of field-effect transistor
EP0064745A3 (de) * 1981-05-07 1983-11-09 Microwave Semiconductor Corp. Verfahren zum Herstellen eines Feldeffekttransistors
JPS58178569A (ja) * 1982-04-12 1983-10-19 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS59195824A (ja) * 1983-04-20 1984-11-07 Sanyo Electric Co Ltd 配線形成方法
JPS61154079A (ja) * 1984-12-26 1986-07-12 Nec Corp 半導体装置の製造方法
JPS6279677A (ja) * 1985-10-03 1987-04-13 Mitsubishi Electric Corp 半導体装置の製造方法
JPS62115782A (ja) * 1985-11-15 1987-05-27 Nec Corp 半導体装置の製造方法
JPS62186568A (ja) * 1986-02-12 1987-08-14 Fujitsu Ltd 半導体装置の製造方法
DE3609274A1 (de) * 1986-03-19 1987-09-24 Siemens Ag Verfahren zur herstellung eines selbstjustiert positionierten metallkontaktes
JPS6356959A (ja) * 1986-08-27 1988-03-11 Nec Corp 電界効果トランジスタの製造方法
JPS6377163A (ja) * 1986-09-19 1988-04-07 Mitsubishi Electric Corp 電界効果トランジスタ
JPS6390171A (ja) * 1986-10-02 1988-04-21 Mitsubishi Electric Corp 電界効果トランジスタの製造方法
JPH0793324B2 (ja) * 1986-12-01 1995-10-09 住友電気工業株式会社 電界効果トランジスタの製造方法
JPS63181477A (ja) * 1987-01-23 1988-07-26 Matsushita Electronics Corp 半導体装置の製造方法
JPS63228671A (ja) * 1987-03-17 1988-09-22 Sanyo Electric Co Ltd 半導体装置の製造方法
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Also Published As

Publication number Publication date
DE69126463D1 (de) 1997-07-17
JP2778600B2 (ja) 1998-07-23
EP0448307B1 (de) 1997-06-11
US5264382A (en) 1993-11-23
KR930010053B1 (ko) 1993-10-14
EP0448307A1 (de) 1991-09-25
JPH03270022A (ja) 1991-12-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee