DE69126073T2 - Halbleiterspeicher mit einer Sequenz getakteter Zugriffskode zum Eintritt in den Prüfmodus - Google Patents

Halbleiterspeicher mit einer Sequenz getakteter Zugriffskode zum Eintritt in den Prüfmodus

Info

Publication number
DE69126073T2
DE69126073T2 DE69126073T DE69126073T DE69126073T2 DE 69126073 T2 DE69126073 T2 DE 69126073T2 DE 69126073 T DE69126073 T DE 69126073T DE 69126073 T DE69126073 T DE 69126073T DE 69126073 T2 DE69126073 T2 DE 69126073T2
Authority
DE
Germany
Prior art keywords
test mode
sequence
power
terminal
special
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69126073T
Other languages
English (en)
Other versions
DE69126073D1 (de
Inventor
William Carl Slemmer
Thomas Allyn Coker
David Charles Mcclure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Application granted granted Critical
Publication of DE69126073D1 publication Critical patent/DE69126073D1/de
Publication of DE69126073T2 publication Critical patent/DE69126073T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Memories (AREA)
DE69126073T 1990-08-17 1991-08-12 Halbleiterspeicher mit einer Sequenz getakteter Zugriffskode zum Eintritt in den Prüfmodus Expired - Fee Related DE69126073T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/570,203 US5072138A (en) 1990-08-17 1990-08-17 Semiconductor memory with sequential clocked access codes for test mode entry

Publications (2)

Publication Number Publication Date
DE69126073D1 DE69126073D1 (de) 1997-06-19
DE69126073T2 true DE69126073T2 (de) 1997-12-11

Family

ID=24278688

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69133365T Expired - Fee Related DE69133365T2 (de) 1990-08-17 1991-08-12 Halbleiterspeicher mit sequenzgetakteten Zugriffscodes zum Eintritt in den Prüfmodus
DE69126073T Expired - Fee Related DE69126073T2 (de) 1990-08-17 1991-08-12 Halbleiterspeicher mit einer Sequenz getakteter Zugriffskode zum Eintritt in den Prüfmodus

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69133365T Expired - Fee Related DE69133365T2 (de) 1990-08-17 1991-08-12 Halbleiterspeicher mit sequenzgetakteten Zugriffscodes zum Eintritt in den Prüfmodus

Country Status (5)

Country Link
US (1) US5072138A (de)
EP (2) EP0471544B1 (de)
JP (1) JP3115036B2 (de)
KR (1) KR100205451B1 (de)
DE (2) DE69133365T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
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DE10066260B4 (de) * 1999-04-30 2013-11-14 Fujitsu Semiconductor Ltd. Halbleiter-Speicheranordnung, Leiterplatte, auf welcher eine Halbleiter-Speicheranordnung montiert ist, und Verfahren zum Testen der Zwischenverbindung zwischen einer Halbleiter-Speicheranordnung und einer Leiterplatte

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JP2557594B2 (ja) * 1992-04-16 1996-11-27 株式会社東芝 半導体記憶装置
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US5406554A (en) * 1993-10-05 1995-04-11 Music Semiconductors, Corp. Synchronous FIFO having an alterable buffer store
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US5629943A (en) * 1993-12-22 1997-05-13 Sgs-Thomson Microelectronics, Inc. Integrated circuit memory with double bitline low special test mode control from output enable
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US5883838A (en) * 1996-01-19 1999-03-16 Stmicroelectronics, Inc. Device and method for driving a conductive path with a signal
US5845059A (en) * 1996-01-19 1998-12-01 Stmicroelectronics, Inc. Data-input device for generating test signals on bit and bit-complement lines
US5619466A (en) * 1996-01-19 1997-04-08 Sgs-Thomson Microelectronics, Inc. Low-power read circuit and method for controlling a sense amplifier
US6144594A (en) * 1996-01-19 2000-11-07 Stmicroelectronics, Inc. Test mode activation and data override
US5848018A (en) * 1996-01-19 1998-12-08 Stmicroelectronics, Inc. Memory-row selector having a test function
US5691950A (en) * 1996-01-19 1997-11-25 Sgs-Thomson Microelectronics, Inc. Device and method for isolating bit lines from a data line
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FR2754100B1 (fr) * 1996-09-30 1998-11-20 Sgs Thomson Microelectronics Memoire a acces serie avec securisation de l'ecriture
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AU7706198A (en) * 1997-05-30 1998-12-30 Micron Technology, Inc. 256 meg dynamic random access memory
US5944845A (en) * 1997-06-26 1999-08-31 Micron Technology, Inc. Circuit and method to prevent inadvertent test mode entry
TW411463B (en) * 1998-06-23 2000-11-11 Nat Science Council Built-in self test for multiple memories in a chip
KR100347068B1 (ko) * 2000-07-20 2002-08-03 삼성전자 주식회사 다른 테스트 모드들에서 동작 가능한 반도체 집적 회로메모리 장치
KR100403955B1 (ko) * 2001-06-01 2003-11-03 주식회사 하이닉스반도체 반도체장치의 테스트모드 제어를 위한 회로 및 방법
DE10151609B4 (de) * 2001-10-18 2013-09-12 Qimonda Ag Schaltung für einen elektronischen Halbleiterbaustein
KR100412142B1 (ko) * 2002-02-26 2003-12-31 주식회사 하이닉스반도체 패킷 전송 방식의 반도체 메모리 장치에서 스페셜 모드를구현하는 회로
JP2003317499A (ja) * 2002-04-26 2003-11-07 Mitsubishi Electric Corp 半導体記憶装置およびそれを用いたメモリシステム
JP4167497B2 (ja) * 2003-01-17 2008-10-15 株式会社ルネサステクノロジ 半導体集積回路及びその試験を行う試験システム
US7157813B2 (en) * 2003-10-03 2007-01-02 Power Integrations, Inc. Method and apparatus for mode selection for high voltage integrated circuits
US7298656B2 (en) * 2004-04-30 2007-11-20 Infineon Technologies Ag Process monitoring by comparing delays proportional to test voltages and reference voltages
JP2006332456A (ja) * 2005-05-27 2006-12-07 Fujitsu Ltd 半導体装置及び試験モード設定方法
JP4262265B2 (ja) * 2006-06-20 2009-05-13 キヤノン株式会社 半導体集積回路
US8407656B2 (en) 2011-06-24 2013-03-26 International Business Machines Corporation Method and structure for a transistor having a relatively large threshold voltage variation range and for a random number generator incorporating multiple essentially identical transistors having such a large threshold voltage variation range
US9506979B2 (en) 2014-04-02 2016-11-29 Freescale Semiconductor, Inc. Test mode entry interlock
US9729128B2 (en) * 2015-04-09 2017-08-08 Synopsys, Inc. Area-delay-power efficient multibit flip-flop
US10222417B1 (en) * 2016-11-28 2019-03-05 Cadence Design Systems, Inc. Securing access to integrated circuit scan mode and data
CN111157872A (zh) * 2019-12-25 2020-05-15 上海亮牛半导体科技有限公司 复用现有逻辑管脚进入测试模式的方法

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10066260B4 (de) * 1999-04-30 2013-11-14 Fujitsu Semiconductor Ltd. Halbleiter-Speicheranordnung, Leiterplatte, auf welcher eine Halbleiter-Speicheranordnung montiert ist, und Verfahren zum Testen der Zwischenverbindung zwischen einer Halbleiter-Speicheranordnung und einer Leiterplatte

Also Published As

Publication number Publication date
EP0471544B1 (de) 1997-05-14
EP0768676A2 (de) 1997-04-16
EP0471544A3 (en) 1993-02-03
DE69133365T2 (de) 2004-12-16
EP0471544A2 (de) 1992-02-19
JP3115036B2 (ja) 2000-12-04
KR920005171A (ko) 1992-03-28
DE69126073D1 (de) 1997-06-19
US5072138A (en) 1991-12-10
EP0768676B1 (de) 2004-02-18
KR100205451B1 (ko) 1999-07-01
DE69133365D1 (de) 2004-03-25
JPH05288806A (ja) 1993-11-05
EP0768676A3 (de) 2001-12-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee