DE69026899D1 - Integriertes Halbleiterschaltungsgerät mit Prüfschaltung - Google Patents

Integriertes Halbleiterschaltungsgerät mit Prüfschaltung

Info

Publication number
DE69026899D1
DE69026899D1 DE69026899T DE69026899T DE69026899D1 DE 69026899 D1 DE69026899 D1 DE 69026899D1 DE 69026899 T DE69026899 T DE 69026899T DE 69026899 T DE69026899 T DE 69026899T DE 69026899 D1 DE69026899 D1 DE 69026899D1
Authority
DE
Germany
Prior art keywords
integrated semiconductor
circuit
circuit device
test
test circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69026899T
Other languages
English (en)
Other versions
DE69026899T2 (de
Inventor
Junichi Shikatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69026899D1 publication Critical patent/DE69026899D1/de
Publication of DE69026899T2 publication Critical patent/DE69026899T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17772—Structural details of configuration resources for powering on or off
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17764—Structural details of configuration resources for reliability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE69026899T 1989-10-13 1990-10-10 Integriertes Halbleiterschaltungsgerät mit Prüfschaltung Expired - Fee Related DE69026899T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1266662A JP2612618B2 (ja) 1989-10-13 1989-10-13 半導体集積回路装置

Publications (2)

Publication Number Publication Date
DE69026899D1 true DE69026899D1 (de) 1996-06-13
DE69026899T2 DE69026899T2 (de) 1996-09-12

Family

ID=17433945

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69026899T Expired - Fee Related DE69026899T2 (de) 1989-10-13 1990-10-10 Integriertes Halbleiterschaltungsgerät mit Prüfschaltung

Country Status (5)

Country Link
US (1) US5369646A (de)
EP (1) EP0422912B1 (de)
JP (1) JP2612618B2 (de)
KR (1) KR940004207B1 (de)
DE (1) DE69026899T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06150024A (ja) * 1992-11-10 1994-05-31 Nec Corp マイクロコンピュータ
US5539331A (en) * 1993-05-10 1996-07-23 Kabushiki Kaisha Toshiba Field programmable gate array having transmission gates and semiconductor integrated circuit for programming connection of wires
EP0655683B1 (de) * 1993-11-30 1999-09-01 STMicroelectronics S.r.l. Schaltungsarchitektur und Verfahren zur Prüfung einer programmierbaren Logikmatrix
US5539349A (en) * 1994-03-24 1996-07-23 Hitachi Microsystems, Inc. Method and apparatus for post-fabrication ascertaining and providing programmable precision timing for sense amplifiers and other circuits
GB9417297D0 (en) * 1994-08-26 1994-10-19 Inmos Ltd Method and apparatus for testing an integrated circuit device
JP3607760B2 (ja) * 1995-10-13 2005-01-05 富士通株式会社 半導体集積回路装置
US5867507A (en) * 1995-12-12 1999-02-02 International Business Machines Corporation Testable programmable gate array and associated LSSD/deterministic test methodology
US5870408A (en) * 1996-04-30 1999-02-09 Sun Microsystems, Inc. Method and apparatus for on die testing
US5991898A (en) 1997-03-10 1999-11-23 Mentor Graphics Corporation Arithmetic built-in self test of multiple scan-based integrated circuits
GB2348753B (en) * 1999-03-27 2003-07-23 Evan Arkas Pulse clock/signal delay apparatus & method
KR100394858B1 (ko) * 2000-12-27 2003-08-19 현대자동차주식회사 캠축 구동용 체인 가이드
KR100440027B1 (ko) * 2002-02-28 2004-07-14 현대자동차주식회사 장력 감쇠를 위한 체인 가이드의 구조
WO2010143336A1 (ja) 2009-06-09 2010-12-16 シャープ株式会社 電子装置
JP2011149775A (ja) * 2010-01-20 2011-08-04 Renesas Electronics Corp 半導体集積回路及びコアテスト回路
US9500700B1 (en) * 2013-11-15 2016-11-22 Xilinx, Inc. Circuits for and methods of testing the operation of an input/output port

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH073865B2 (ja) * 1984-08-07 1995-01-18 富士通株式会社 半導体集積回路及び半導体集積回路の試験方法
JPH0772744B2 (ja) * 1984-09-04 1995-08-02 株式会社日立製作所 半導体集積回路装置
US4730320A (en) * 1985-02-07 1988-03-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
EP0197363B1 (de) * 1985-03-26 1990-05-30 Siemens Aktiengesellschaft Verfahren zum Betreiben eines Halbleiterspeichers mit integrierter Paralleltestmöglichkeit und Auswerteschaltung zur Durchführung des Verfahrens
JPH0672911B2 (ja) * 1985-05-29 1994-09-14 株式会社東芝 システムｌｓｉ
JPS61294695A (ja) * 1985-06-20 1986-12-25 Mitsubishi Electric Corp 半導体集積回路装置
US4739250A (en) * 1985-11-20 1988-04-19 Fujitsu Limited Semiconductor integrated circuit device with test circuit
US4857774A (en) * 1986-09-19 1989-08-15 Actel Corporation Testing apparatus and diagnostic method for use with programmable interconnect architecture
JPS63293944A (ja) * 1987-05-27 1988-11-30 Nec Corp 論理回路代替方式
US5065090A (en) * 1988-07-13 1991-11-12 Cross-Check Technology, Inc. Method for testing integrated circuits having a grid-based, "cross-check" te

Also Published As

Publication number Publication date
EP0422912A2 (de) 1991-04-17
US5369646A (en) 1994-11-29
DE69026899T2 (de) 1996-09-12
JP2612618B2 (ja) 1997-05-21
EP0422912A3 (en) 1992-05-27
EP0422912B1 (de) 1996-05-08
JPH03127853A (ja) 1991-05-30
KR910008424A (ko) 1991-05-31
KR940004207B1 (ko) 1994-05-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee