DE69022644D1 - Steuerschaltung für den Datenausgang für eine Halbleiterspeicheranordnung. - Google Patents

Steuerschaltung für den Datenausgang für eine Halbleiterspeicheranordnung.

Info

Publication number
DE69022644D1
DE69022644D1 DE69022644T DE69022644T DE69022644D1 DE 69022644 D1 DE69022644 D1 DE 69022644D1 DE 69022644 T DE69022644 T DE 69022644T DE 69022644 T DE69022644 T DE 69022644T DE 69022644 D1 DE69022644 D1 DE 69022644D1
Authority
DE
Germany
Prior art keywords
control circuit
memory device
semiconductor memory
data output
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69022644T
Other languages
English (en)
Other versions
DE69022644T2 (de
Inventor
Masami Masuda
Kenichi Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69022644D1 publication Critical patent/DE69022644D1/de
Application granted granted Critical
Publication of DE69022644T2 publication Critical patent/DE69022644T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE69022644T 1989-07-12 1990-07-12 Steuerschaltung für den Datenausgang für eine Halbleiterspeicheranordnung. Expired - Fee Related DE69022644T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1179814A JPH0344890A (ja) 1989-07-12 1989-07-12 半導体記憶装置のデータ出力制御回路

Publications (2)

Publication Number Publication Date
DE69022644D1 true DE69022644D1 (de) 1995-11-02
DE69022644T2 DE69022644T2 (de) 1996-04-11

Family

ID=16072356

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69022644T Expired - Fee Related DE69022644T2 (de) 1989-07-12 1990-07-12 Steuerschaltung für den Datenausgang für eine Halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US5073872A (de)
EP (1) EP0408032B1 (de)
JP (1) JPH0344890A (de)
KR (1) KR930002255B1 (de)
DE (1) DE69022644T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5311471A (en) * 1989-11-27 1994-05-10 Kabushiki Kaisha Toshiba Semiconductor memory device
JP2573392B2 (ja) * 1990-03-30 1997-01-22 株式会社東芝 半導体記憶装置
JPH0834060B2 (ja) * 1990-06-22 1996-03-29 株式会社東芝 半導体記憶装置
US5255222A (en) * 1991-01-23 1993-10-19 Ramtron International Corporation Output control circuit having continuously variable drive current
US5239506A (en) * 1991-02-04 1993-08-24 International Business Machines Corporation Latch and data out driver for memory arrays
US5278803A (en) * 1991-09-11 1994-01-11 Compaq Computer Corporation Memory column address strobe buffer and synchronization and data latch interlock
DE69227436T2 (de) * 1991-12-17 1999-04-15 Sgs-Thomson Microelectronics, Inc., Carrollton, Tex. Integrierte Schaltung mit gegenseitig gesteuerten differenzialen Datenleitungen
JPH05250872A (ja) * 1992-03-09 1993-09-28 Oki Electric Ind Co Ltd ランダム・アクセス・メモリ
JP2803466B2 (ja) * 1992-04-28 1998-09-24 日本電気株式会社 半導体記憶装置の救済方法
US5306963A (en) * 1992-06-19 1994-04-26 Intel Corporation Address transition detection noise filter in pulse summation circuit for nonvolatile semiconductor memory
US5418479A (en) * 1993-12-27 1995-05-23 Intel Corporation Method and circuitry for generating a safe address transition pulse in a memory device
US5471157A (en) * 1994-03-31 1995-11-28 Sgs-Thomson Microelectronics, Inc. Integrated circuit with centralized control of edge transition detection pulse generation
KR0172798B1 (ko) * 1995-06-30 1999-03-30 김주용 모드 적응형 데이타 출력 버퍼
US5689462A (en) * 1995-12-22 1997-11-18 Townsend And Townsend And Crew, Llp Parallel output buffers in memory circuits
JP3192077B2 (ja) * 1996-01-30 2001-07-23 日本電気株式会社 半導体記憶装置
KR100278988B1 (ko) * 1998-02-25 2001-02-01 김영환 어드레스 천이 검출회로
US6285627B1 (en) * 2000-04-25 2001-09-04 Advanced Micro Devices, Inc. Address transition detector architecture for a high density flash memory device
JP2005032020A (ja) * 2003-07-07 2005-02-03 Matsushita Electric Ind Co Ltd 記憶装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61172294A (ja) * 1985-01-28 1986-08-02 Seiko Epson Corp 半導体記憶装置
JPH0612626B2 (ja) * 1986-01-22 1994-02-16 株式会社日立製作所 半導体メモリ装置
JPH0612631B2 (ja) * 1986-10-17 1994-02-16 日本電気株式会社 半導体メモリ
JPH0612632B2 (ja) * 1987-02-27 1994-02-16 日本電気株式会社 メモリ回路
JPH0799639B2 (ja) * 1987-07-31 1995-10-25 株式会社東芝 半導体集積回路
JPS6489097A (en) * 1987-09-30 1989-04-03 Toshiba Corp Semiconductor integrated circuit
US4959816A (en) * 1987-12-28 1990-09-25 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
JPH0661160B2 (ja) * 1987-12-28 1994-08-10 株式会社東芝 半導体集積回路
JPH02226589A (ja) * 1989-02-27 1990-09-10 Nec Corp 半導体記憶装置

Also Published As

Publication number Publication date
EP0408032B1 (de) 1995-09-27
EP0408032A3 (en) 1992-08-05
US5073872A (en) 1991-12-17
EP0408032A2 (de) 1991-01-16
JPH0344890A (ja) 1991-02-26
KR910003666A (ko) 1991-02-28
DE69022644T2 (de) 1996-04-11
KR930002255B1 (ko) 1993-03-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee