DE68929483D1 - Datenprozessor mit einer Befehlseinheit, die einen Cachespeicher und einen ROM aufweist. - Google Patents

Datenprozessor mit einer Befehlseinheit, die einen Cachespeicher und einen ROM aufweist.

Info

Publication number
DE68929483D1
DE68929483D1 DE68929483T DE68929483T DE68929483D1 DE 68929483 D1 DE68929483 D1 DE 68929483D1 DE 68929483 T DE68929483 T DE 68929483T DE 68929483 T DE68929483 T DE 68929483T DE 68929483 D1 DE68929483 D1 DE 68929483D1
Authority
DE
Germany
Prior art keywords
rom
cache memory
data processor
instruction unit
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68929483T
Other languages
English (en)
Other versions
DE68929483T2 (de
Inventor
Takashi Hotta
Shigeya Tanaka
Hideo Maejima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE68929483D1 publication Critical patent/DE68929483D1/de
Publication of DE68929483T2 publication Critical patent/DE68929483T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
DE68929483T 1988-11-11 1989-11-10 Datenprozessor mit einer Befehlseinheit, die einen Cachespeicher und einen ROM aufweist. Expired - Fee Related DE68929483T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63283673A JP2810068B2 (ja) 1988-11-11 1988-11-11 プロセッサシステム、コンピュータシステム及び命令処理方法
JP28367388 1988-11-11

Publications (2)

Publication Number Publication Date
DE68929483D1 true DE68929483D1 (de) 2003-09-18
DE68929483T2 DE68929483T2 (de) 2004-07-01

Family

ID=17668583

Family Applications (3)

Application Number Title Priority Date Filing Date
DE68928340T Expired - Fee Related DE68928340T2 (de) 1988-11-11 1989-11-10 Fliessband-Datenprozessor
DE68929483T Expired - Fee Related DE68929483T2 (de) 1988-11-11 1989-11-10 Datenprozessor mit einer Befehlseinheit, die einen Cachespeicher und einen ROM aufweist.
DE68929215T Expired - Fee Related DE68929215T2 (de) 1988-11-11 1989-11-10 Datenprozessor

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE68928340T Expired - Fee Related DE68928340T2 (de) 1988-11-11 1989-11-10 Fliessband-Datenprozessor

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE68929215T Expired - Fee Related DE68929215T2 (de) 1988-11-11 1989-11-10 Datenprozessor

Country Status (5)

Country Link
US (3) US5233694A (de)
EP (3) EP0368332B1 (de)
JP (1) JP2810068B2 (de)
KR (2) KR0149658B1 (de)
DE (3) DE68928340T2 (de)

Families Citing this family (101)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504932A (en) * 1990-05-04 1996-04-02 International Business Machines Corporation System for executing scalar instructions in parallel based on control bits appended by compounding decoder
DE69130588T2 (de) * 1990-05-29 1999-05-27 National Semiconductor Corp., Santa Clara, Calif. Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür
JP2834292B2 (ja) * 1990-08-15 1998-12-09 株式会社日立製作所 データ・プロセッサ
JPH04111127A (ja) * 1990-08-31 1992-04-13 Toshiba Corp 演算処理装置
JP2532300B2 (ja) * 1990-10-17 1996-09-11 三菱電機株式会社 並列処理装置における命令供給装置
JP2682232B2 (ja) * 1990-11-21 1997-11-26 松下電器産業株式会社 浮動小数点演算処理装置
EP0488819B1 (de) * 1990-11-30 1999-01-13 Kabushiki Kaisha Toshiba Ausführungsvorrichtung für bedingte Verzweigungsbefehle
RU1804645C (ru) * 1991-03-27 1993-03-23 Институт Точной Механики И Вычислительной Техники Им.С.А.Лебедева Центральный процессор
US5488729A (en) * 1991-05-15 1996-01-30 Ross Technology, Inc. Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution
JP2984463B2 (ja) * 1991-06-24 1999-11-29 株式会社日立製作所 マイクロコンピュータ
JP3105197B2 (ja) 1991-06-24 2000-10-30 株式会社日立製作所 除算回路及び除算方法
EP0547240B1 (de) * 1991-07-08 2000-01-12 Seiko Epson Corporation Risc-mikroprozessorarchitektur mit schnellem unterbrechungs- und ausnahmemodus
EP1526446A3 (de) * 1991-07-08 2007-04-04 Seiko Epson Corporation RISC-Prozessor mit erweiterbarer Architektur
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
JP2875909B2 (ja) * 1991-07-12 1999-03-31 三菱電機株式会社 並列演算処理装置
JPH0546386A (ja) * 1991-08-13 1993-02-26 Hitachi Ltd データプロセツサ
GB9123271D0 (en) * 1991-11-02 1991-12-18 Int Computers Ltd Data processing system
EP0551090B1 (de) * 1992-01-06 1999-08-04 Hitachi, Ltd. Rechner mit einer Parallelverarbeitungsfähigkeit
GB2263565B (en) * 1992-01-23 1995-08-30 Intel Corp Microprocessor with apparatus for parallel execution of instructions
DE4237417C2 (de) * 1992-03-25 1997-01-30 Hewlett Packard Co Datenverarbeitungssystem
EP0636256B1 (de) 1992-03-31 1997-06-04 Seiko Epson Corporation Befehlsablauffolgeplanung von einem risc-superskalarprozessor
US5438668A (en) 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
US5371864A (en) * 1992-04-09 1994-12-06 International Business Machines Corporation Apparatus for concurrent multiple instruction decode in variable length instruction set computer
EP0638183B1 (de) 1992-05-01 1997-03-05 Seiko Epson Corporation Vorrichtung und verfahren zum befehlsabschluss in einem superskalaren prozessor.
US5416913A (en) * 1992-07-27 1995-05-16 Intel Corporation Method and apparatus for dependency checking in a multi-pipelined microprocessor
US6735685B1 (en) * 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
KR100248903B1 (ko) * 1992-09-29 2000-03-15 야스카와 히데아키 수퍼스칼라마이크로프로세서에서의 적재 및 저장연산처리방법 및 시스템
DE69330889T2 (de) 1992-12-31 2002-03-28 Seiko Epson Corp., Tokio/Tokyo System und Verfahren zur Änderung der Namen von Registern
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
JP3182591B2 (ja) * 1993-01-20 2001-07-03 株式会社日立製作所 マイクロプロセッサ
US5416911A (en) * 1993-02-02 1995-05-16 International Business Machines Corporation Performance enhancement for load multiple register instruction
US5673409A (en) * 1993-03-31 1997-09-30 Vlsi Technology, Inc. Self-defining instruction size
US5560025A (en) * 1993-03-31 1996-09-24 Intel Corporation Entry allocation apparatus and method of same
US5463748A (en) 1993-06-30 1995-10-31 Intel Corporation Instruction buffer for aligning instruction sets using boundary detection
CA2123442A1 (en) * 1993-09-20 1995-03-21 David S. Ray Multiple execution unit dispatch with instruction dependency
US5878245A (en) 1993-10-29 1999-03-02 Advanced Micro Devices, Inc. High performance load/store functional unit and data cache
DE69434669T2 (de) * 1993-10-29 2006-10-12 Advanced Micro Devices, Inc., Sunnyvale Spekulative Befehlswarteschlange für Befehle mit variabler Byteslänge
EP0651332B1 (de) * 1993-10-29 2001-07-18 Advanced Micro Devices, Inc. Linearadressierter Mikroprozessorcachespeicher
EP0651320B1 (de) * 1993-10-29 2001-05-23 Advanced Micro Devices, Inc. Superskalarbefehlsdekoder
US5630082A (en) * 1993-10-29 1997-05-13 Advanced Micro Devices, Inc. Apparatus and method for instruction queue scanning
US5689672A (en) * 1993-10-29 1997-11-18 Advanced Micro Devices, Inc. Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
US5604909A (en) 1993-12-15 1997-02-18 Silicon Graphics Computer Systems, Inc. Apparatus for processing instructions in a computing system
US5974534A (en) * 1994-02-14 1999-10-26 Hewlett-Packard Company Predecoding and steering mechanism for instructions in a superscalar processor
US5586277A (en) * 1994-03-01 1996-12-17 Intel Corporation Method for parallel steering of fixed length fields containing a variable length instruction from an instruction buffer to parallel decoders
US5600806A (en) * 1994-03-01 1997-02-04 Intel Corporation Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer
US5566298A (en) * 1994-03-01 1996-10-15 Intel Corporation Method for state recovery during assist and restart in a decoder having an alias mechanism
US5537629A (en) * 1994-03-01 1996-07-16 Intel Corporation Decoder for single cycle decoding of single prefixes in variable length instructions
US5630083A (en) * 1994-03-01 1997-05-13 Intel Corporation Decoder for decoding multiple instructions in parallel
US5559974A (en) * 1994-03-01 1996-09-24 Intel Corporation Decoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operation
US5673427A (en) * 1994-03-01 1997-09-30 Intel Corporation Packing valid micro operations received from a parallel decoder into adjacent locations of an output queue
US5608885A (en) * 1994-03-01 1997-03-04 Intel Corporation Method for handling instructions from a branch prior to instruction decoding in a computer which executes variable-length instructions
US5758116A (en) * 1994-09-30 1998-05-26 Intel Corporation Instruction length decoder for generating output length indicia to identity boundaries between variable length instructions
US5901302A (en) * 1995-01-25 1999-05-04 Advanced Micro Devices, Inc. Superscalar microprocessor having symmetrical, fixed issue positions each configured to execute a particular subset of instructions
US6237082B1 (en) 1995-01-25 2001-05-22 Advanced Micro Devices, Inc. Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received
JP3180175B2 (ja) * 1995-02-13 2001-06-25 株式会社日立製作所 命令レベルの並列処理制御方法およびプロセッサ
US5737550A (en) * 1995-03-28 1998-04-07 Advanced Micro Devices, Inc. Cache memory to processor bus interface and method thereof
US5859991A (en) * 1995-06-07 1999-01-12 Advanced Micro Devices, Inc. Parallel and scalable method for identifying valid instructions and a superscalar microprocessor including an instruction scanning unit employing the method
US5867701A (en) * 1995-06-12 1999-02-02 Intel Corporation System for inserting a supplemental micro-operation flow into a macroinstruction-generated micro-operation flow
US5926642A (en) 1995-10-06 1999-07-20 Advanced Micro Devices, Inc. RISC86 instruction set
US5706489A (en) * 1995-10-18 1998-01-06 International Business Machines Corporation Method for a CPU to utilize a parallel instruction execution processing facility for assisting in the processing of the accessed data
US5796974A (en) * 1995-11-07 1998-08-18 Advanced Micro Devices, Inc. Microcode patching apparatus and method
US5815724A (en) * 1996-03-29 1998-09-29 Intel Corporation Method and apparatus for controlling power consumption in a microprocessor
US6131152A (en) * 1996-05-15 2000-10-10 Philips Electronics North America Corporation Planar cache layout and instruction stream therefor
WO1997043715A2 (en) * 1996-05-15 1997-11-20 Philips Electronics N.V. Processor with an instruction cache
US5862398A (en) * 1996-05-15 1999-01-19 Philips Electronics North America Corporation Compiler generating swizzled instructions usable in a simplified cache layout
JPH1011289A (ja) * 1996-06-19 1998-01-16 Mitsubishi Electric Corp 並列処理プロセッサにおける命令数拡張方法および並列処理プロセッサ
US5890219A (en) * 1996-11-27 1999-03-30 Emc Corporation Redundant writing of data to cached storage system
US5884055A (en) * 1996-11-27 1999-03-16 Emc Corporation Method and apparatus including a shared resource and multiple processors running a common control program accessing the shared resource
US5890207A (en) * 1996-11-27 1999-03-30 Emc Corporation High performance integrated cached storage device
US5852727A (en) * 1997-03-10 1998-12-22 Advanced Micro Devices, Inc. Instruction scanning unit for locating instructions via parallel scanning of start and end byte information
TW373149B (en) 1997-07-02 1999-11-01 Matsushita Electric Ind Co Ltd Program control method
US6467035B2 (en) * 1997-09-08 2002-10-15 Agere Systems Guardian Corp. System and method for performing table look-ups using a multiple data fetch architecture
JP2954119B2 (ja) * 1997-11-26 1999-09-27 日本電気株式会社 命令実行サイクル可変回路
DE19802364A1 (de) * 1998-01-22 1999-07-29 Siemens Ag Vorrichtung und Verfahren zur Steuerung von Prozessen auf einem Computersystem
DE19819531C1 (de) * 1998-04-30 1999-12-02 Siemens Ag RISC-Prozessor mit einer Debug-Schnittstelleneinheit
US6233690B1 (en) * 1998-09-17 2001-05-15 Intel Corporation Mechanism for saving power on long latency stalls
US6668316B1 (en) * 1999-02-17 2003-12-23 Elbrus International Limited Method and apparatus for conflict-free execution of integer and floating-point operations with a common register file
EP1050808B1 (de) * 1999-05-03 2008-04-30 STMicroelectronics S.A. Befehlausgabe in einem Rechner
EP1050809A1 (de) * 1999-05-03 2000-11-08 STMicroelectronics SA Befehlsabhängigkeit in einem Rechner
US6442677B1 (en) * 1999-06-10 2002-08-27 Advanced Micro Devices, Inc. Apparatus and method for superforwarding load operands in a microprocessor
US7149878B1 (en) * 2000-10-30 2006-12-12 Mips Technologies, Inc. Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values
US7711926B2 (en) 2001-04-18 2010-05-04 Mips Technologies, Inc. Mapping system and method for instruction set processing
US6826681B2 (en) 2001-06-18 2004-11-30 Mips Technologies, Inc. Instruction specified register value saving in allocated caller stack or not yet allocated callee stack
US7107439B2 (en) * 2001-08-10 2006-09-12 Mips Technologies, Inc. System and method of controlling software decompression through exceptions
EP1387253B1 (de) * 2002-07-31 2017-09-20 Texas Instruments Incorporated Dynamische Übersetzung und Befehlsausführung in einem Prozessor
US7366352B2 (en) * 2003-03-20 2008-04-29 International Business Machines Corporation Method and apparatus for performing fast closest match in pattern recognition
US7698539B1 (en) 2003-07-16 2010-04-13 Banning John P System and method of instruction modification
US6996916B2 (en) * 2004-03-09 2006-02-14 Helen Of Troy Limited Variable ion hair styling appliances
US20050224091A1 (en) * 2004-04-08 2005-10-13 Helen Of Troy Limited Ion curling iron and straightener
WO2006051962A1 (ja) * 2004-11-12 2006-05-18 Justsystems Corporation データ処理装置およびデータ処理方法
DE602006013810D1 (de) 2005-04-22 2010-06-02 Mitsubishi Chem Corp Aus biomasseressourcen gewonnener polyester und herstellungsverfahren dafür
ATE466331T1 (de) * 2006-09-06 2010-05-15 Silicon Hive Bv Datenverarbeitungsschaltung mit mehreren anweisungsarten, verfahren zum betrieb einer solchen datenschaltung und scheduling-verfahren für eine solche datenschaltung
US9513959B2 (en) * 2007-11-21 2016-12-06 Arm Limited Contention management for a hardware transactional memory
US20090138890A1 (en) * 2007-11-21 2009-05-28 Arm Limited Contention management for a hardware transactional memory
SE536462C2 (sv) * 2011-10-18 2013-11-26 Mediatek Sweden Ab Digital signalprocessor och basbandskommunikationsanordning
JP6106499B2 (ja) * 2013-04-11 2017-03-29 株式会社日立製作所 データ反映方法
US11599358B1 (en) 2021-08-12 2023-03-07 Tenstorrent Inc. Pre-staged instruction registers for variable length instruction set machine
US12067395B2 (en) 2021-08-12 2024-08-20 Tenstorrent Inc. Pre-staged instruction registers for variable length instruction set machine
KR102449203B1 (ko) 2022-03-08 2022-09-29 주식회사 제이비티 안전상태정보 관리 방법

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573853A (en) * 1968-12-04 1971-04-06 Texas Instruments Inc Look-ahead control for operation of program loops
US3614745A (en) * 1969-09-15 1971-10-19 Ibm Apparatus and method in a multiple operand stream computing system for identifying the specification of multitasks situations and controlling the execution thereof
US3771138A (en) * 1971-08-31 1973-11-06 Ibm Apparatus and method for serializing instructions from two independent instruction streams
US4521850A (en) * 1977-12-30 1985-06-04 Honeywell Information Systems Inc. Instruction buffer associated with a cache memory unit
JPS6043535B2 (ja) 1979-12-29 1985-09-28 富士通株式会社 情報処理装置
US4616331A (en) * 1980-02-25 1986-10-07 Tsuneo Kinoshita Information processing system consisting of an arithmetic control unit formed into a one-chip typed by application of a highly-integrated semiconductor device
JPS6028015B2 (ja) * 1980-08-28 1985-07-02 日本電気株式会社 情報処理装置
US4437149A (en) 1980-11-17 1984-03-13 International Business Machines Corporation Cache memory architecture with decoding
EP0072373B1 (de) * 1981-08-19 1986-03-19 International Business Machines Corporation Mikroprozessor
EP0082903B1 (de) * 1981-12-29 1987-05-13 International Business Machines Corporation Steuergerät mit Anschlussmöglichkeit an zwei Speicher unterschiedlicher Geschwindigkeit
JPS5932045A (ja) * 1982-08-16 1984-02-21 Hitachi Ltd 情報処理装置
US4928223A (en) * 1982-10-06 1990-05-22 Fairchild Semiconductor Corporation Floating point microprocessor with directable two level microinstructions
US4546428A (en) * 1983-03-08 1985-10-08 International Telephone & Telegraph Corporation Associative array with transversal horizontal multiplexers
US4594655A (en) * 1983-03-14 1986-06-10 International Business Machines Corporation (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions
JPS59186062A (ja) * 1983-04-07 1984-10-22 Nec Corp 分散形プロセツサシステム
JPS6015746A (ja) * 1983-07-08 1985-01-26 Hitachi Ltd デ−タ処理装置
JPS60120439A (ja) * 1983-12-05 1985-06-27 Nec Corp 演算処理装置
JPS60136872A (ja) 1983-12-26 1985-07-20 Hitachi Ltd ベクトル処理装置
US4599708A (en) * 1983-12-30 1986-07-08 International Business Machines Corporation Method and structure for machine data storage with simultaneous write and read
AU553416B2 (en) * 1984-02-24 1986-07-17 Fujitsu Limited Pipeline processing
US4873629A (en) * 1984-06-20 1989-10-10 Convex Computer Corporation Instruction processing unit for computer
US4620275A (en) * 1984-06-20 1986-10-28 Wallach Steven J Computer system
JPS619734A (ja) * 1984-06-26 1986-01-17 Nec Corp プロセツサ制御方式
US4766564A (en) * 1984-08-13 1988-08-23 International Business Machines Corporation Dual putaway/bypass busses for multiple arithmetic units
US4677545A (en) * 1984-10-12 1987-06-30 American Telephone And Telegraph Company Microprocessor having macro-rom and main program queues
US4794517A (en) * 1985-04-15 1988-12-27 International Business Machines Corporation Three phased pipelined signal processor
US4789925A (en) * 1985-07-31 1988-12-06 Unisys Corporation Vector data logical usage conflict detection
DE3751503T2 (de) 1986-03-26 1996-05-09 Hitachi Ltd Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen.
US4722050A (en) * 1986-03-27 1988-01-26 Hewlett-Packard Company Method and apparatus for facilitating instruction processing of a digital computer
US4825360A (en) * 1986-07-30 1989-04-25 Symbolics, Inc. System and method for parallel processing with mostly functional languages
US4766566A (en) * 1986-08-18 1988-08-23 International Business Machines Corp. Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing
JPS6373332A (ja) 1986-09-16 1988-04-02 Nec Corp マイクロプログラム制御方式
JPS63131230A (ja) * 1986-11-21 1988-06-03 Hitachi Ltd 情報処理装置
JPH0810430B2 (ja) 1986-11-28 1996-01-31 株式会社日立製作所 情報処理装置
US4811296A (en) * 1987-05-15 1989-03-07 Analog Devices, Inc. Multi-port register file with flow-through of data
US5101341A (en) * 1988-08-25 1992-03-31 Edgcore Technology, Inc. Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
US5072364A (en) * 1989-05-24 1991-12-10 Tandem Computers Incorporated Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel
JP2550213B2 (ja) 1989-07-07 1996-11-06 株式会社日立製作所 並列処理装置および並列処理方法
JPH03288246A (ja) 1990-04-04 1991-12-18 Matsushita Electric Ind Co Ltd 命令キャッシュメモリ
US5214763A (en) 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
DE69130588T2 (de) 1990-05-29 1999-05-27 National Semiconductor Corp., Santa Clara, Calif. Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür

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EP0782071A3 (de) 1997-07-30
DE68929215D1 (de) 2000-06-29
DE68929215T2 (de) 2001-01-25
KR0160602B1 (ko) 1999-10-01
US20010021970A1 (en) 2001-09-13
JPH02130634A (ja) 1990-05-18
DE68929483T2 (de) 2004-07-01
EP0368332A3 (de) 1992-07-15
DE68928340T2 (de) 1998-02-12
KR900008394A (ko) 1990-06-04
US5233694A (en) 1993-08-03
DE68928340D1 (de) 1997-10-30
KR0149658B1 (ko) 1998-10-15
EP0782071A2 (de) 1997-07-02
EP0368332A2 (de) 1990-05-16
US6256726B1 (en) 2001-07-03
EP0782071B1 (de) 2000-05-24
EP0996057B1 (de) 2003-08-13
US7424598B2 (en) 2008-09-09
EP0368332B1 (de) 1997-09-24
JP2810068B2 (ja) 1998-10-15
EP0996057A1 (de) 2000-04-26

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