DE69130588T2 - Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür - Google Patents

Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür

Info

Publication number
DE69130588T2
DE69130588T2 DE69130588T DE69130588T DE69130588T2 DE 69130588 T2 DE69130588 T2 DE 69130588T2 DE 69130588 T DE69130588 T DE 69130588T DE 69130588 T DE69130588 T DE 69130588T DE 69130588 T2 DE69130588 T2 DE 69130588T2
Authority
DE
Germany
Prior art keywords
method therefor
instruction cache
decoded instruction
partially decoded
partially
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69130588T
Other languages
English (en)
Other versions
DE69130588D1 (de
Inventor
Donald B Alpert
Dror Avnon
Amos Ben-Meir
Ran Talmudi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of DE69130588D1 publication Critical patent/DE69130588D1/de
Application granted granted Critical
Publication of DE69130588T2 publication Critical patent/DE69130588T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
DE69130588T 1990-05-29 1991-05-16 Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür Expired - Fee Related DE69130588T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US52986990A 1990-05-29 1990-05-29

Publications (2)

Publication Number Publication Date
DE69130588D1 DE69130588D1 (de) 1999-01-21
DE69130588T2 true DE69130588T2 (de) 1999-05-27

Family

ID=24111573

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130588T Expired - Fee Related DE69130588T2 (de) 1990-05-29 1991-05-16 Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür

Country Status (4)

Country Link
US (2) US5481751A (de)
EP (1) EP0459232B1 (de)
JP (1) JP3186798B2 (de)
DE (1) DE69130588T2 (de)

Families Citing this family (197)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2810068B2 (ja) 1988-11-11 1998-10-15 株式会社日立製作所 プロセッサシステム、コンピュータシステム及び命令処理方法
US5295249A (en) * 1990-05-04 1994-03-15 International Business Machines Corporation Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel
EP0650612B1 (de) * 1992-03-25 1999-08-18 Zilog Incorporated Schnelle befehlsdekodierung in einem pipeline-prozessor
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
US5974508A (en) * 1992-07-31 1999-10-26 Fujitsu Limited Cache memory system and method for automatically locking cache entries to prevent selected memory items from being replaced
EP0586057B1 (de) * 1992-08-31 2000-03-01 Sun Microsystems, Inc. Schnelles Vorausholen und Zuteilung von Befehlen mittels vorausschauender Anmerkungen von früher vorausgeholten
JP3417984B2 (ja) * 1993-09-10 2003-06-16 株式会社日立製作所 キャッシュ競合削減コンパイル方法
DE69427734T2 (de) * 1993-10-29 2002-05-23 Advanced Micro Devices Inc Linearadressierter Mikroprozessorcachespeicher
US5630082A (en) * 1993-10-29 1997-05-13 Advanced Micro Devices, Inc. Apparatus and method for instruction queue scanning
US5689672A (en) * 1993-10-29 1997-11-18 Advanced Micro Devices, Inc. Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
US5878245A (en) 1993-10-29 1999-03-02 Advanced Micro Devices, Inc. High performance load/store functional unit and data cache
EP0651320B1 (de) * 1993-10-29 2001-05-23 Advanced Micro Devices, Inc. Superskalarbefehlsdekoder
DE69434669T2 (de) * 1993-10-29 2006-10-12 Advanced Micro Devices, Inc., Sunnyvale Spekulative Befehlswarteschlange für Befehle mit variabler Byteslänge
US5510934A (en) * 1993-12-15 1996-04-23 Silicon Graphics, Inc. Memory system including local and global caches for storing floating point and integer data
US5974534A (en) * 1994-02-14 1999-10-26 Hewlett-Packard Company Predecoding and steering mechanism for instructions in a superscalar processor
US5878244A (en) * 1995-01-25 1999-03-02 Advanced Micro Devices, Inc. Reorder buffer configured to allocate storage capable of storing results corresponding to a maximum number of concurrently receivable instructions regardless of a number of instructions received
US5901302A (en) * 1995-01-25 1999-05-04 Advanced Micro Devices, Inc. Superscalar microprocessor having symmetrical, fixed issue positions each configured to execute a particular subset of instructions
US5819057A (en) * 1995-01-25 1998-10-06 Advanced Micro Devices, Inc. Superscalar microprocessor including an instruction alignment unit with limited dispatch to decode units
US5832249A (en) * 1995-01-25 1998-11-03 Advanced Micro Devices, Inc. High performance superscalar alignment unit
US6237082B1 (en) 1995-01-25 2001-05-22 Advanced Micro Devices, Inc. Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received
US5742784A (en) * 1995-01-25 1998-04-21 International Business Machines Corporation System for reordering of instructions before placement into cache to reduce dispatch latency
US5903741A (en) * 1995-01-25 1999-05-11 Advanced Micro Devices, Inc. Method of allocating a fixed reorder buffer storage line for execution results regardless of a number of concurrently dispatched instructions
US6006324A (en) * 1995-01-25 1999-12-21 Advanced Micro Devices, Inc. High performance superscalar alignment unit
US5632028A (en) * 1995-03-03 1997-05-20 Hal Computer Systems, Inc. Hardware support for fast software emulation of unimplemented instructions
US5737550A (en) * 1995-03-28 1998-04-07 Advanced Micro Devices, Inc. Cache memory to processor bus interface and method thereof
US5758114A (en) * 1995-04-12 1998-05-26 Advanced Micro Devices, Inc. High speed instruction alignment unit for aligning variable byte-length instructions according to predecode information in a superscalar microprocessor
US5887152A (en) * 1995-04-12 1999-03-23 Advanced Micro Devices, Inc. Load/store unit with multiple oldest outstanding instruction pointers for completing store and load/store miss instructions
US5819059A (en) * 1995-04-12 1998-10-06 Advanced Micro Devices, Inc. Predecode unit adapted for variable byte-length instruction set processors and method of operating the same
US5802588A (en) * 1995-04-12 1998-09-01 Advanced Micro Devices, Inc. Load/store unit implementing non-blocking loads for a superscalar microprocessor and method of selecting loads in a non-blocking fashion from a load/store buffer
US5764946A (en) * 1995-04-12 1998-06-09 Advanced Micro Devices Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address
US5991869A (en) * 1995-04-12 1999-11-23 Advanced Micro Devices, Inc. Superscalar microprocessor including a high speed instruction alignment unit
US5832297A (en) * 1995-04-12 1998-11-03 Advanced Micro Devices, Inc. Superscalar microprocessor load/store unit employing a unified buffer and separate pointers for load and store operations
US5822574A (en) * 1995-04-12 1998-10-13 Advanced Micro Devices, Inc. Functional unit with a pointer for mispredicted resolution, and a superscalar microprocessor employing the same
US5835753A (en) * 1995-04-12 1998-11-10 Advanced Micro Devices, Inc. Microprocessor with dynamically extendable pipeline stages and a classifying circuit
US5822558A (en) * 1995-04-12 1998-10-13 Advanced Micro Devices, Inc. Method and apparatus for predecoding variable byte-length instructions within a superscalar microprocessor
US5900012A (en) * 1995-05-10 1999-05-04 Advanced Micro Devices, Inc. Storage device having varying access times and a superscalar microprocessor employing the same
US5875315A (en) * 1995-06-07 1999-02-23 Advanced Micro Devices, Inc. Parallel and scalable instruction scanning unit
US5680578A (en) * 1995-06-07 1997-10-21 Advanced Micro Devices, Inc. Microprocessor using an instruction field to specify expanded functionality and a computer system employing same
US5768610A (en) * 1995-06-07 1998-06-16 Advanced Micro Devices, Inc. Lookahead register value generator and a superscalar microprocessor employing same
US5822778A (en) * 1995-06-07 1998-10-13 Advanced Micro Devices, Inc. Microprocessor and method of using a segment override prefix instruction field to expand the register file
US5768574A (en) * 1995-06-07 1998-06-16 Advanced Micro Devices, Inc. Microprocessor using an instruction field to expand the condition flags and a computer system employing the microprocessor
US5875324A (en) * 1995-06-07 1999-02-23 Advanced Micro Devices, Inc. Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock
US5859991A (en) * 1995-06-07 1999-01-12 Advanced Micro Devices, Inc. Parallel and scalable method for identifying valid instructions and a superscalar microprocessor including an instruction scanning unit employing the method
US5761712A (en) * 1995-06-07 1998-06-02 Advanced Micro Devices Data memory unit and method for storing data into a lockable cache in one clock cycle by previewing the tag array
US5878255A (en) * 1995-06-07 1999-03-02 Advanced Micro Devices, Inc. Update unit for providing a delayed update to a branch prediction array
US6604190B1 (en) 1995-06-07 2003-08-05 Advanced Micro Devices, Inc. Data address prediction structure and a method for operating the same
US5826071A (en) * 1995-08-31 1998-10-20 Advanced Micro Devices, Inc. Parallel mask decoder and method for generating said mask
US5781789A (en) * 1995-08-31 1998-07-14 Advanced Micro Devices, Inc. Superscaler microprocessor employing a parallel mask decoder
US5893146A (en) * 1995-08-31 1999-04-06 Advanced Micro Design, Inc. Cache structure having a reduced tag comparison to enable data transfer from said cache
US5987561A (en) 1995-08-31 1999-11-16 Advanced Micro Devices, Inc. Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle
US5860104A (en) * 1995-08-31 1999-01-12 Advanced Micro Devices, Inc. Data cache which speculatively updates a predicted data cache storage location with store data and subsequently corrects mispredicted updates
US5752069A (en) * 1995-08-31 1998-05-12 Advanced Micro Devices, Inc. Superscalar microprocessor employing away prediction structure
US5845323A (en) * 1995-08-31 1998-12-01 Advanced Micro Devices, Inc. Way prediction structure for predicting the way of a cache in which an access hits, thereby speeding cache access time
US5854921A (en) * 1995-08-31 1998-12-29 Advanced Micro Devices, Inc. Stride-based data address prediction structure
US5809273A (en) * 1996-01-26 1998-09-15 Advanced Micro Devices, Inc. Instruction predecode and multiple instruction decode
US5872947A (en) * 1995-10-24 1999-02-16 Advanced Micro Devices, Inc. Instruction classification circuit configured to classify instructions into a plurality of instruction types prior to decoding said instructions
US5892936A (en) * 1995-10-30 1999-04-06 Advanced Micro Devices, Inc. Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register
US5933618A (en) * 1995-10-30 1999-08-03 Advanced Micro Devices, Inc. Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurrently recorded instruction
US5881278A (en) * 1995-10-30 1999-03-09 Advanced Micro Devices, Inc. Return address prediction system which adjusts the contents of return stack storage to enable continued prediction after a mispredicted branch
US5796974A (en) * 1995-11-07 1998-08-18 Advanced Micro Devices, Inc. Microcode patching apparatus and method
US5835744A (en) * 1995-11-20 1998-11-10 Advanced Micro Devices, Inc. Microprocessor configured to swap operands in order to minimize dependency checking logic
US5787474A (en) * 1995-11-20 1998-07-28 Advanced Micro Devices, Inc. Dependency checking structure for a pair of caches which are accessed from different pipeline stages of an instruction processing pipeline
US5903910A (en) * 1995-11-20 1999-05-11 Advanced Micro Devices, Inc. Method for transferring data between a pair of caches configured to be accessed from different stages of an instruction processing pipeline
US5765035A (en) * 1995-11-20 1998-06-09 Advanced Micro Devices, Inc. Recorder buffer capable of detecting dependencies between accesses to a pair of caches
US5864707A (en) * 1995-12-11 1999-01-26 Advanced Micro Devices, Inc. Superscalar microprocessor configured to predict return addresses from a return stack storage
US5819080A (en) * 1996-01-02 1998-10-06 Advanced Micro Devices, Inc. Microprocessor using an instruction field to specify condition flags for use with branch instructions and a computer system employing the microprocessor
US5930490A (en) * 1996-01-02 1999-07-27 Advanced Micro Devices, Inc. Microprocessor configured to switch instruction sets upon detection of a plurality of consecutive instructions
US5822559A (en) * 1996-01-02 1998-10-13 Advanced Micro Devices, Inc. Apparatus and method for aligning variable byte-length instructions to a plurality of issue positions
US5742791A (en) 1996-02-14 1998-04-21 Advanced Micro Devices, Inc. Apparatus for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor
US5787266A (en) * 1996-02-20 1998-07-28 Advanced Micro Devices, Inc. Apparatus and method for accessing special registers without serialization
US5848287A (en) 1996-02-20 1998-12-08 Advanced Micro Devices, Inc. Superscalar microprocessor including a reorder buffer which detects dependencies between accesses to a pair of caches
US5687110A (en) * 1996-02-20 1997-11-11 Advanced Micro Devices, Inc. Array having an update circuit for updating a storage location with a value stored in another storage location
US5715425A (en) * 1996-02-22 1998-02-03 Sun Microsystems, Inc. Apparatus and method for prefetching data into an external cache
US5790821A (en) 1996-03-08 1998-08-04 Advanced Micro Devices, Inc. Control bit vector storage for storing control vectors corresponding to instruction operations in a microprocessor
US5813033A (en) * 1996-03-08 1998-09-22 Advanced Micro Devices, Inc. Superscalar microprocessor including a cache configured to detect dependencies between accesses to the cache and another cache
US5752259A (en) * 1996-03-26 1998-05-12 Advanced Micro Devices, Inc. Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache
US5838943A (en) * 1996-03-26 1998-11-17 Advanced Micro Devices, Inc. Apparatus for speculatively storing and restoring data to a cache memory
US5835968A (en) * 1996-04-17 1998-11-10 Advanced Micro Devices, Inc. Apparatus for providing memory and register operands concurrently to functional units
US6085302A (en) * 1996-04-17 2000-07-04 Advanced Micro Devices, Inc. Microprocessor having address generation units for efficient generation of memory operation addresses
US5835511A (en) * 1996-05-17 1998-11-10 Advanced Micro Devices, Inc. Method and mechanism for checking integrity of byte enable signals
US6108769A (en) 1996-05-17 2000-08-22 Advanced Micro Devices, Inc. Dependency table for reducing dependency checking hardware
US5748978A (en) * 1996-05-17 1998-05-05 Advanced Micro Devices, Inc. Byte queue divided into multiple subqueues for optimizing instruction selection logic
US5918056A (en) * 1996-05-17 1999-06-29 Advanced Micro Devices, Inc. Segmentation suspend mode for real-time interrupt support
US5822560A (en) * 1996-05-23 1998-10-13 Advanced Micro Devices, Inc. Apparatus for efficient instruction execution via variable issue and variable control vectors per issue
US6006320A (en) * 1996-07-01 1999-12-21 Sun Microsystems, Inc. Processor architecture with independent OS resources
US6049863A (en) * 1996-07-24 2000-04-11 Advanced Micro Devices, Inc. Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor
US5867680A (en) * 1996-07-24 1999-02-02 Advanced Micro Devices, Inc. Microprocessor configured to simultaneously dispatch microcode and directly-decoded instructions
US5813045A (en) * 1996-07-24 1998-09-22 Advanced Micro Devices, Inc. Conditional early data address generation mechanism for a microprocessor
US5903740A (en) * 1996-07-24 1999-05-11 Advanced Micro Devices, Inc. Apparatus and method for retiring instructions in excess of the number of accessible write ports
US5872951A (en) * 1996-07-26 1999-02-16 Advanced Micro Design, Inc. Reorder buffer having a future file for storing speculative instruction execution results
US5872943A (en) * 1996-07-26 1999-02-16 Advanced Micro Devices, Inc. Apparatus for aligning instructions using predecoded shift amounts
US5915110A (en) * 1996-07-26 1999-06-22 Advanced Micro Devices, Inc. Branch misprediction recovery in a reorder buffer having a future file
US5946468A (en) * 1996-07-26 1999-08-31 Advanced Micro Devices, Inc. Reorder buffer having an improved future file for storing speculative instruction execution results
US5900013A (en) * 1996-07-26 1999-05-04 Advanced Micro Devices, Inc. Dual comparator scheme for detecting a wrap-around condition and generating a cancel signal for removing wrap-around buffer entries
US5765016A (en) * 1996-09-12 1998-06-09 Advanced Micro Devices, Inc. Reorder buffer configured to store both speculative and committed register states
US5822575A (en) * 1996-09-12 1998-10-13 Advanced Micro Devices, Inc. Branch prediction storage for storing branch prediction information such that a corresponding tag may be routed with the branch instruction
US5794028A (en) * 1996-10-17 1998-08-11 Advanced Micro Devices, Inc. Shared branch prediction structure
US5870579A (en) * 1996-11-18 1999-02-09 Advanced Micro Devices, Inc. Reorder buffer including a circuit for selecting a designated mask corresponding to an instruction that results in an exception
US5920710A (en) * 1996-11-18 1999-07-06 Advanced Micro Devices, Inc. Apparatus and method for modifying status bits in a reorder buffer with a large speculative state
US5978906A (en) 1996-11-19 1999-11-02 Advanced Micro Devices, Inc. Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions
US5954816A (en) * 1996-11-19 1999-09-21 Advanced Micro Devices, Inc. Branch selector prediction
US5995749A (en) * 1996-11-19 1999-11-30 Advanced Micro Devices, Inc. Branch prediction mechanism employing branch selectors to select a branch prediction
US6175906B1 (en) 1996-12-06 2001-01-16 Advanced Micro Devices, Inc. Mechanism for fast revalidation of virtual tags
US5887160A (en) * 1996-12-10 1999-03-23 Fujitsu Limited Method and apparatus for communicating integer and floating point data over a shared data path in a single instruction pipeline processor
US5870580A (en) * 1996-12-13 1999-02-09 Advanced Micro Devices, Inc. Decoupled forwarding reorder buffer configured to allocate storage in chunks for instructions having unresolved dependencies
US5881305A (en) * 1996-12-13 1999-03-09 Advanced Micro Devices, Inc. Register rename stack for a microprocessor
JPH10232779A (ja) * 1997-01-24 1998-09-02 Texas Instr Inc <Ti> 命令並列処理方法及び装置
US5923862A (en) * 1997-01-28 1999-07-13 Samsung Electronics Co., Ltd. Processor that decodes a multi-cycle instruction into single-cycle micro-instructions and schedules execution of the micro-instructions
US5983321A (en) * 1997-03-12 1999-11-09 Advanced Micro Devices, Inc. Cache holding register for receiving instruction packets and for providing the instruction packets to a predecode unit and instruction cache
US5862065A (en) * 1997-02-13 1999-01-19 Advanced Micro Devices, Inc. Method and circuit for fast generation of zero flag condition code in a microprocessor-based computer
US5768555A (en) * 1997-02-20 1998-06-16 Advanced Micro Devices, Inc. Reorder buffer employing last in buffer and last in line bits
US6141740A (en) * 1997-03-03 2000-10-31 Advanced Micro Devices, Inc. Apparatus and method for microcode patching for generating a next address
US6233672B1 (en) 1997-03-06 2001-05-15 Advanced Micro Devices, Inc. Piping rounding mode bits with floating point instructions to eliminate serialization
US5968163A (en) 1997-03-10 1999-10-19 Advanced Micro Devices, Inc. Microcode scan unit for scanning microcode instructions using predecode data
US5852727A (en) * 1997-03-10 1998-12-22 Advanced Micro Devices, Inc. Instruction scanning unit for locating instructions via parallel scanning of start and end byte information
US5850532A (en) * 1997-03-10 1998-12-15 Advanced Micro Devices, Inc. Invalid instruction scan unit for detecting invalid predecode data corresponding to instructions being fetched
US5859992A (en) * 1997-03-12 1999-01-12 Advanced Micro Devices, Inc. Instruction alignment using a dispatch list and a latch list
US5859998A (en) * 1997-03-19 1999-01-12 Advanced Micro Devices, Inc. Hierarchical microcode implementation of floating point instructions for a microprocessor
US5828873A (en) * 1997-03-19 1998-10-27 Advanced Micro Devices, Inc. Assembly queue for a floating point unit
US5930492A (en) * 1997-03-19 1999-07-27 Advanced Micro Devices, Inc. Rapid pipeline control using a control word and a steering word
US5887185A (en) * 1997-03-19 1999-03-23 Advanced Micro Devices, Inc. Interface for coupling a floating point unit to a reorder buffer
US5963723A (en) * 1997-03-26 1999-10-05 International Business Machines Corporation System for pairing dependent instructions having non-contiguous addresses during dispatch
US5987235A (en) * 1997-04-04 1999-11-16 Advanced Micro Devices, Inc. Method and apparatus for predecoding variable byte length instructions for fast scanning of instructions
TW384445B (en) * 1997-04-11 2000-03-11 Ibm Method for bursting processor data to or from an I/O device
US5901076A (en) * 1997-04-16 1999-05-04 Advanced Micro Designs, Inc. Ripple carry shifter in a floating point arithmetic unit of a microprocessor
US6003128A (en) * 1997-05-01 1999-12-14 Advanced Micro Devices, Inc. Number of pipeline stages and loop length related counter differential based end-loop prediction
US6122729A (en) * 1997-05-13 2000-09-19 Advanced Micro Devices, Inc. Prefetch buffer which stores a pointer indicating an initial predecode position
US5845101A (en) * 1997-05-13 1998-12-01 Advanced Micro Devices, Inc. Prefetch buffer for storing instructions prior to placing the instructions in an instruction cache
US5872946A (en) * 1997-06-11 1999-02-16 Advanced Micro Devices, Inc. Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch
US5940602A (en) * 1997-06-11 1999-08-17 Advanced Micro Devices, Inc. Method and apparatus for predecoding variable byte length instructions for scanning of a number of RISC operations
US6009511A (en) * 1997-06-11 1999-12-28 Advanced Micro Devices, Inc. Apparatus and method for tagging floating point operands and results for rapid detection of special floating point numbers
US6073230A (en) * 1997-06-11 2000-06-06 Advanced Micro Devices, Inc. Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches
US5933629A (en) * 1997-06-12 1999-08-03 Advanced Micro Devices, Inc. Apparatus and method for detecting microbranches early
US5983337A (en) * 1997-06-12 1999-11-09 Advanced Micro Devices, Inc. Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction
US5898865A (en) * 1997-06-12 1999-04-27 Advanced Micro Devices, Inc. Apparatus and method for predicting an end of loop for string instructions
US5933626A (en) * 1997-06-12 1999-08-03 Advanced Micro Devices, Inc. Apparatus and method for tracing microprocessor instructions
US6012125A (en) * 1997-06-20 2000-01-04 Advanced Micro Devices, Inc. Superscalar microprocessor including a decoded instruction cache configured to receive partially decoded instructions
US5948098A (en) * 1997-06-30 1999-09-07 Sun Microsystems, Inc. Execution unit and method for executing performance critical and non-performance critical arithmetic instructions in separate pipelines
US5978901A (en) * 1997-08-21 1999-11-02 Advanced Micro Devices, Inc. Floating point and multimedia unit with data type reclassification capability
US6101577A (en) * 1997-09-15 2000-08-08 Advanced Micro Devices, Inc. Pipelined instruction cache and branch prediction mechanism therefor
US5931943A (en) * 1997-10-21 1999-08-03 Advanced Micro Devices, Inc. Floating point NaN comparison
US6185675B1 (en) 1997-10-24 2001-02-06 Advanced Micro Devices, Inc. Basic block oriented trace cache utilizing a basic block sequence buffer to indicate program order of cached basic blocks
US6032252A (en) * 1997-10-28 2000-02-29 Advanced Micro Devices, Inc. Apparatus and method for efficient loop control in a superscalar microprocessor
US5974542A (en) * 1997-10-30 1999-10-26 Advanced Micro Devices, Inc. Branch prediction unit which approximates a larger number of branch predictions using a smaller number of branch predictions and an alternate target indication
US6230259B1 (en) 1997-10-31 2001-05-08 Advanced Micro Devices, Inc. Transparent extended state save
US6157996A (en) * 1997-11-13 2000-12-05 Advanced Micro Devices, Inc. Processor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register space
US6199154B1 (en) 1997-11-17 2001-03-06 Advanced Micro Devices, Inc. Selecting cache to fetch in multi-level cache system based on fetch address source and pre-fetching additional data to the cache for future access
US6079003A (en) 1997-11-20 2000-06-20 Advanced Micro Devices, Inc. Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache
US6516395B1 (en) 1997-11-20 2003-02-04 Advanced Micro Devices, Inc. System and method for controlling access to a privilege-partitioned address space with a fixed set of attributes
US6154818A (en) * 1997-11-20 2000-11-28 Advanced Micro Devices, Inc. System and method of controlling access to privilege partitioned address space for a model specific register file
US6079005A (en) * 1997-11-20 2000-06-20 Advanced Micro Devices, Inc. Microprocessor including virtual address branch prediction and current page register to provide page portion of virtual and physical fetch address
US5974432A (en) * 1997-12-05 1999-10-26 Advanced Micro Devices, Inc. On-the-fly one-hot encoding of leading zero count
GB2332075B (en) * 1997-12-06 2002-08-07 Mitel Corp Optimized instruction storage and distribution for parallel processors architectures
US5870578A (en) * 1997-12-09 1999-02-09 Advanced Micro Devices, Inc. Workload balancing in a microprocessor for reduced instruction dispatch stalling
US6097716A (en) * 1997-12-12 2000-08-01 Lucent Technologies Inc. Rate detection for multi-rate communications
US6016545A (en) * 1997-12-16 2000-01-18 Advanced Micro Devices, Inc. Reduced size storage apparatus for storing cache-line-related data in a high frequency microprocessor
US6016533A (en) * 1997-12-16 2000-01-18 Advanced Micro Devices, Inc. Way prediction logic for cache array
US6157986A (en) * 1997-12-16 2000-12-05 Advanced Micro Devices, Inc. Fast linear tag validation unit for use in microprocessor
US6112296A (en) * 1997-12-18 2000-08-29 Advanced Micro Devices, Inc. Floating point stack manipulation using a register map and speculative top of stack values
US6018798A (en) * 1997-12-18 2000-01-25 Advanced Micro Devices, Inc. Floating point unit using a central window for storing instructions capable of executing multiple instructions in a single clock cycle
US6112018A (en) * 1997-12-18 2000-08-29 Advanced Micro Devices, Inc. Apparatus for exchanging two stack registers
US6175908B1 (en) 1998-04-30 2001-01-16 Advanced Micro Devices, Inc. Variable byte-length instructions using state of function bit of second byte of plurality of instructions bytes as indicative of whether first byte is a prefix byte
US6141745A (en) * 1998-04-30 2000-10-31 Advanced Micro Devices, Inc. Functional bit identifying a prefix byte via a particular state regardless of type of instruction
US6256727B1 (en) 1998-05-12 2001-07-03 International Business Machines Corporation Method and system for fetching noncontiguous instructions in a single clock cycle
SG83719A1 (en) * 1998-05-21 2001-10-16 Texas Instruments Inc Method and system for buffering instructions in a processor
US6275924B1 (en) 1998-09-15 2001-08-14 Texas Instruments Incorporated System for buffering instructions in a processor by reissuing instruction fetches during decoder stall time
US6230262B1 (en) 1998-07-31 2001-05-08 Advanced Micro Devices, Inc. Processor configured to selectively free physical registers upon retirement of instructions
US6122656A (en) * 1998-07-31 2000-09-19 Advanced Micro Devices, Inc. Processor configured to map logical register numbers to physical register numbers using virtual register numbers
US6119223A (en) * 1998-07-31 2000-09-12 Advanced Micro Devices, Inc. Map unit having rapid misprediction recovery
US6339822B1 (en) 1998-10-02 2002-01-15 Advanced Micro Devices, Inc. Using padded instructions in a block-oriented cache
US6223254B1 (en) * 1998-12-04 2001-04-24 Stmicroelectronics, Inc. Parcel cache
US6647490B2 (en) 1999-10-14 2003-11-11 Advanced Micro Devices, Inc. Training line predictor for branch targets
US6636959B1 (en) 1999-10-14 2003-10-21 Advanced Micro Devices, Inc. Predictor miss decoder updating line predictor storing instruction fetch address and alignment information upon instruction decode termination condition
US6546478B1 (en) 1999-10-14 2003-04-08 Advanced Micro Devices, Inc. Line predictor entry with location pointers and control information for corresponding instructions in a cache line
US6351802B1 (en) * 1999-12-03 2002-02-26 Intel Corporation Method and apparatus for constructing a pre-scheduled instruction cache
US6848024B1 (en) 2000-08-07 2005-01-25 Broadcom Corporation Programmably disabling one or more cache entries
US6748492B1 (en) 2000-08-07 2004-06-08 Broadcom Corporation Deterministic setting of replacement policy in a cache through way selection
US6732234B1 (en) 2000-08-07 2004-05-04 Broadcom Corporation Direct access mode for a cache
US6981132B2 (en) 2000-08-09 2005-12-27 Advanced Micro Devices, Inc. Uniform register addressing using prefix byte
US6877084B1 (en) 2000-08-09 2005-04-05 Advanced Micro Devices, Inc. Central processing unit (CPU) accessing an extended register set in an extended register mode
US6738792B1 (en) 2001-03-09 2004-05-18 Advanced Micro Devices, Inc. Parallel mask generator
US6748495B2 (en) 2001-05-15 2004-06-08 Broadcom Corporation Random generator
GB2381602B (en) 2001-10-12 2004-04-14 Siroyan Ltd Early resolving instructions
US20030196072A1 (en) * 2002-04-11 2003-10-16 Chinnakonda Murali S. Digital signal processor architecture for high computation speed
US7266587B2 (en) 2002-05-15 2007-09-04 Broadcom Corporation System having interfaces, switch, and memory bridge for CC-NUMA operation
JP2004013602A (ja) * 2002-06-07 2004-01-15 Handotai Rikougaku Kenkyu Center:Kk データ駆動プロセッサのエミュレーションシステム
GB2393274B (en) * 2002-09-20 2006-03-15 Advanced Risc Mach Ltd Data processing system having an external instruction set and an internal instruction set
US7117290B2 (en) 2003-09-03 2006-10-03 Advanced Micro Devices, Inc. MicroTLB and micro tag for reducing power in a processor
US20050138331A1 (en) * 2003-12-22 2005-06-23 Alberola Carl A. Direct memory access unit with instruction pre-decoder
US7685410B2 (en) 2007-02-13 2010-03-23 Global Foundries Inc. Redirect recovery cache that receives branch misprediction redirects and caches instructions to be dispatched in response to the redirects
US8578387B1 (en) * 2007-07-31 2013-11-05 Nvidia Corporation Dynamic load balancing of instructions for execution by heterogeneous processing engines
US9304775B1 (en) 2007-11-05 2016-04-05 Nvidia Corporation Dispatching of instructions for execution by heterogeneous processing engines
US9124233B2 (en) * 2010-08-25 2015-09-01 Vixs Systems, Inc Audio equalizer and methods for use therewith
US9430243B2 (en) 2012-04-30 2016-08-30 Apple Inc. Optimizing register initialization operations
US9405690B2 (en) 2013-08-07 2016-08-02 Oracle International Corporation Method for storing modified instruction data in a shared cache
US10311191B2 (en) 2017-01-26 2019-06-04 Advanced Micro Devices, Inc. Memory including side-car arrays with irregular sized entries
US11100001B2 (en) 2017-05-04 2021-08-24 Sisense Ltd. Techniques for improving space utilization in a cache

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4589087A (en) * 1983-06-30 1986-05-13 International Business Machines Corporation Condition register architecture for a primitive instruction set machine
US4620275A (en) * 1984-06-20 1986-10-28 Wallach Steven J Computer system
US4873629A (en) * 1984-06-20 1989-10-10 Convex Computer Corporation Instruction processing unit for computer
US4646233A (en) * 1984-06-20 1987-02-24 Weatherford James R Physical cache unit for computer
EP0239081B1 (de) * 1986-03-26 1995-09-06 Hitachi, Ltd. Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen
US4766566A (en) * 1986-08-18 1988-08-23 International Business Machines Corp. Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing
US4933837A (en) * 1986-12-01 1990-06-12 Advanced Micro Devices, Inc. Methods and apparatus for optimizing instruction processing in computer systems employing a combination of instruction cache and high speed consecutive transfer memories
US5050070A (en) * 1988-02-29 1991-09-17 Convex Computer Corporation Multi-processor computer system having self-allocating processors
US5202967A (en) * 1988-08-09 1993-04-13 Matsushita Electric Industrial Co., Ltd. Data processing apparatus for performing parallel decoding and parallel execution of a variable word length instruction
US5101341A (en) * 1988-08-25 1992-03-31 Edgcore Technology, Inc. Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
US5050068A (en) * 1988-10-03 1991-09-17 Duke University Method and apparatus for using extracted program flow information to prepare for execution multiple instruction streams
US5051885A (en) * 1988-10-07 1991-09-24 Hewlett-Packard Company Data processing system for concurrent dispatch of instructions to multiple functional units
JP2810068B2 (ja) * 1988-11-11 1998-10-15 株式会社日立製作所 プロセッサシステム、コンピュータシステム及び命令処理方法
US5129067A (en) * 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements

Also Published As

Publication number Publication date
JP3186798B2 (ja) 2001-07-11
US5669011A (en) 1997-09-16
EP0459232B1 (de) 1998-12-09
US5481751A (en) 1996-01-02
DE69130588D1 (de) 1999-01-21
EP0459232A2 (de) 1991-12-04
JPH0553795A (ja) 1993-03-05
EP0459232A3 (en) 1992-04-15

Similar Documents

Publication Publication Date Title
DE69130588T2 (de) Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür
DE69125711D1 (de) Hochreflektive biogitter und verfahren
DE69229198D1 (de) Verzweigungsbefehlprozessor und Verfahren
DE69522423T2 (de) Digitalisierstift und Verfahren
DE69128741D1 (de) Mehrstufiger Befehlscachespeicher und Verwendungsverfahren dafür
DE69330634D1 (de) Tragbarer Rechner und Verfahren
FI961365A0 (fi) Osittainen hapetusmenetelmä
DE69413031T2 (de) Robuster sprachprozessor und verfahren
DE69406920D1 (de) Analyt-reagierende ktp zusammensetzung und verfahren
FI940870A (fi) Puhdistusmenetelmä ja -laite
DE69414001T2 (de) Bestimmungsmethode
DE69518212T2 (de) Anzeigeverfahren von Schlüssel-im-Zündschloss
DE69430617T2 (de) Dekoder und verfahren zur dekodierung
DE69407640T2 (de) Gefriervorrichtung und -verfahren
DE69411159D1 (de) Strömungsleitende drehkupplung und verfahren
DK0750589T3 (da) Reduktion af tilbageværende chloridindhold i jernoxider
NO932286D0 (no) Stereoselektiv anion-glykosyleringsprosess
DE69132201D1 (de) Speicher-Anordnung und Verfahren mit Vorausholungspuffer
KR900700406A (ko) 석면처리제 및 처리법
DE69330813D1 (de) Bildprozessor und verfahren dafuer
DE69514960D1 (de) Schlackbehandlungssystem und -methode
MX9101773A (es) Aparato y metodo de refrigeracion
DE69129358T2 (de) Verfahren und System zur Cachesteuerung
DE69529809D1 (de) Dekodierungsverfahren und -vorrichtung
NO942643D0 (no) Demodulator og fremgangsmåte derved

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee