DE69132201D1 - Speicher-Anordnung und Verfahren mit Vorausholungspuffer - Google Patents
Speicher-Anordnung und Verfahren mit VorausholungspufferInfo
- Publication number
- DE69132201D1 DE69132201D1 DE69132201T DE69132201T DE69132201D1 DE 69132201 D1 DE69132201 D1 DE 69132201D1 DE 69132201 T DE69132201 T DE 69132201T DE 69132201 T DE69132201 T DE 69132201T DE 69132201 D1 DE69132201 D1 DE 69132201D1
- Authority
- DE
- Germany
- Prior art keywords
- memory arrangement
- prefetch buffer
- prefetch
- buffer
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02B—INTERNAL-COMBUSTION PISTON ENGINES; COMBUSTION ENGINES IN GENERAL
- F02B75/00—Other engines
- F02B75/02—Engines characterised by their cycles, e.g. six-stroke
- F02B2075/022—Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle
- F02B2075/027—Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle four
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/6022—Using a prefetch buffer or dedicated prefetch cache
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US50006290A | 1990-03-27 | 1990-03-27 | |
US07/499,958 US5261066A (en) | 1990-03-27 | 1990-03-27 | Data processing system and method with small fully-associative cache and prefetch buffers |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69132201D1 true DE69132201D1 (de) | 2000-06-21 |
DE69132201T2 DE69132201T2 (de) | 2000-12-28 |
Family
ID=27053366
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69132201T Expired - Lifetime DE69132201T2 (de) | 1990-03-27 | 1991-03-25 | Speicher-Anordnung und Verfahren mit Vorausholungspuffer |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0449540B1 (de) |
JP (1) | JPH04270431A (de) |
KR (1) | KR930011345B1 (de) |
DE (1) | DE69132201T2 (de) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1993018459A1 (en) * | 1992-03-06 | 1993-09-16 | Rambus Inc. | Prefetching into a cache to minimize main memory access time and cache size in a computer system |
JPH06110781A (ja) * | 1992-09-30 | 1994-04-22 | Nec Corp | キャッシュメモリ装置 |
JPH06222990A (ja) * | 1992-10-16 | 1994-08-12 | Fujitsu Ltd | データ処理装置 |
US5848432A (en) | 1993-08-05 | 1998-12-08 | Hitachi, Ltd. | Data processor with variable types of cache memories |
TW228580B (en) * | 1993-10-01 | 1994-08-21 | Ibm | Information processing system and method of operation |
US5603004A (en) * | 1994-02-14 | 1997-02-11 | Hewlett-Packard Company | Method for decreasing time penalty resulting from a cache miss in a multi-level cache system |
KR0146059B1 (ko) * | 1995-04-11 | 1998-09-15 | 문정환 | 미참조 선인출 캐쉬를 이용한 명령어 선인출 방법 및 그 회로 |
JP3068469B2 (ja) | 1996-08-28 | 2000-07-24 | 新潟日本電気株式会社 | 2次レベルキャッシュメモリシステム |
US6085292A (en) * | 1997-06-05 | 2000-07-04 | Digital Equipment Corporation | Apparatus and method for providing non-blocking pipelined cache |
GB2348024B (en) * | 1999-03-16 | 2003-06-25 | Ibm | Cache memory systems |
JP3956698B2 (ja) * | 1999-07-07 | 2007-08-08 | 株式会社日立製作所 | メモリ制御装置 |
US6901500B1 (en) * | 2000-07-28 | 2005-05-31 | Silicon Graphics, Inc. | Method and apparatus for prefetching information and storing the information in a stream buffer |
DE102004007614A1 (de) * | 2004-02-17 | 2005-09-01 | Giesecke & Devrient Gmbh | Datenträger mit Ablaufdiagnosespeicher |
JP2009230374A (ja) * | 2008-03-21 | 2009-10-08 | Fujitsu Ltd | 情報処理装置,プログラム,及び命令列生成方法 |
JP5348146B2 (ja) | 2009-01-28 | 2013-11-20 | 日本電気株式会社 | キャッシュメモリおよびその制御方法 |
GB2493192A (en) * | 2011-07-28 | 2013-01-30 | St Microelectronics Res & Dev | An exclusive cache arrangement |
JP5724981B2 (ja) * | 2012-09-26 | 2015-05-27 | 日本電気株式会社 | メモリアクセス制御装置、メモリアクセス制御システム、及び、メモリアクセス制御方法 |
US9037835B1 (en) * | 2013-10-24 | 2015-05-19 | Arm Limited | Data processing method and apparatus for prefetching |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53134335A (en) * | 1977-04-28 | 1978-11-22 | Fujitsu Ltd | Memory control system |
JPS629436A (ja) * | 1985-07-05 | 1987-01-17 | Nec Corp | マイクロプログラム制御装置 |
JPS6267649A (ja) * | 1985-09-19 | 1987-03-27 | Nec Corp | キヤツシユメモリ制御装置におけるストア処理方式 |
US4853846A (en) * | 1986-07-29 | 1989-08-01 | Intel Corporation | Bus expander with logic for virtualizing single cache control into dual channels with separate directories and prefetch for different processors |
GB2200483B (en) * | 1987-01-22 | 1991-10-16 | Nat Semiconductor Corp | Memory referencing in a high performance microprocessor |
EP0375864A3 (de) * | 1988-12-29 | 1991-03-20 | International Business Machines Corporation | Cache-Speicherumgehung |
-
1991
- 1991-03-25 EP EP91302555A patent/EP0449540B1/de not_active Expired - Lifetime
- 1991-03-25 DE DE69132201T patent/DE69132201T2/de not_active Expired - Lifetime
- 1991-03-27 JP JP3085843A patent/JPH04270431A/ja active Pending
- 1991-03-27 KR KR1019910004914A patent/KR930011345B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
EP0449540A2 (de) | 1991-10-02 |
EP0449540B1 (de) | 2000-05-17 |
EP0449540A3 (en) | 1992-09-09 |
DE69132201T2 (de) | 2000-12-28 |
KR930011345B1 (ko) | 1993-11-30 |
JPH04270431A (ja) | 1992-09-25 |
KR910017286A (ko) | 1991-11-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8327 | Change in the person/name/address of the patent owner |
Owner name: COMPAQ COMPUTER CORP., HOUSTON, TEX., US |
|
8364 | No opposition during term of opposition |