SG83719A1 - Method and system for buffering instructions in a processor - Google Patents

Method and system for buffering instructions in a processor

Info

Publication number
SG83719A1
SG83719A1 SG9902542A SG1999002542A SG83719A1 SG 83719 A1 SG83719 A1 SG 83719A1 SG 9902542 A SG9902542 A SG 9902542A SG 1999002542 A SG1999002542 A SG 1999002542A SG 83719 A1 SG83719 A1 SG 83719A1
Authority
SG
Singapore
Prior art keywords
processor
buffering instructions
buffering
instructions
Prior art date
Application number
SG9902542A
Inventor
Chandar G Subash
Deepak Mital
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/153,370 external-priority patent/US6275924B1/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of SG83719A1 publication Critical patent/SG83719A1/en

Links

SG9902542A 1998-05-21 1999-05-21 Method and system for buffering instructions in a processor SG83719A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IN1998MA1998 1998-05-21
US09/153,370 US6275924B1 (en) 1998-09-15 1998-09-15 System for buffering instructions in a processor by reissuing instruction fetches during decoder stall time

Publications (1)

Publication Number Publication Date
SG83719A1 true SG83719A1 (en) 2001-10-16

Family

ID=26324864

Family Applications (1)

Application Number Title Priority Date Filing Date
SG9902542A SG83719A1 (en) 1998-05-21 1999-05-21 Method and system for buffering instructions in a processor

Country Status (2)

Country Link
JP (1) JP3798180B2 (en)
SG (1) SG83719A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0459232A2 (en) * 1990-05-29 1991-12-04 National Semiconductor Corporation Partially decoded instruction cache
US5101341A (en) * 1988-08-25 1992-03-31 Edgcore Technology, Inc. Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
US5586295A (en) * 1993-01-21 1996-12-17 Advanced Micro Devices, Inc. Combination prefetch buffer and instruction cache

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5101341A (en) * 1988-08-25 1992-03-31 Edgcore Technology, Inc. Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
EP0459232A2 (en) * 1990-05-29 1991-12-04 National Semiconductor Corporation Partially decoded instruction cache
US5586295A (en) * 1993-01-21 1996-12-17 Advanced Micro Devices, Inc. Combination prefetch buffer and instruction cache

Also Published As

Publication number Publication date
JP2000148479A (en) 2000-05-30
JP3798180B2 (en) 2006-07-19

Similar Documents

Publication Publication Date Title
GB2343270B (en) Method and apparatus for branch instruction processing in a processor
GB2341061B (en) Method and system for authenticating a user
GB2352548B (en) Method and apparatus for executing standard functions in a computer system
AU1175602A (en) Method and system for automatically publishing content
GB2358937B (en) Method and system for natural language understanding
AU2345400A (en) Electronic non-repudiation system and method
HK1045777A1 (en) System and method for miniguide implementation
AU2001257417A1 (en) Method and system for providing a flexible and efficient processor for use in graphics processing
EP1146813A4 (en) System and method for executing a treatment regimen
AU4078299A (en) Method and system for secure transactions in a computer system
IL127073A0 (en) Software translation system and method
GB0028079D0 (en) System and method
GB0021378D0 (en) Method and system for natural language understanding
EP0923197A4 (en) Processor and processing method
HK1039842A1 (en) Method and system in a telecommunication system
GB9921235D0 (en) A system and method for navigating through source content
GB2359136B (en) Device and method for alignment
EP0724213A3 (en) A method and system for reducing dispatch latency in a processor
AU2897001A (en) Method and processor in a telecommunication system
EP1325424A4 (en) Method and system for assembling concurrently-generated content
HK1042953A1 (en) A thermal processing system and method including a mosk
IL110960A0 (en) System and method for hitting a target in a cluster
GB9818344D0 (en) Method and system for object validation
GB9921616D0 (en) System and method for processing a call in a cellular system
AU2001280045A1 (en) Method and system for ensuring approved weighing