DE68928308D1 - Verfahren zum Herstellen von integrierten Halbleiterschaltungen in der Universalschaltkreistechnik - Google Patents

Verfahren zum Herstellen von integrierten Halbleiterschaltungen in der Universalschaltkreistechnik

Info

Publication number
DE68928308D1
DE68928308D1 DE68928308T DE68928308T DE68928308D1 DE 68928308 D1 DE68928308 D1 DE 68928308D1 DE 68928308 T DE68928308 T DE 68928308T DE 68928308 T DE68928308 T DE 68928308T DE 68928308 D1 DE68928308 D1 DE 68928308D1
Authority
DE
Germany
Prior art keywords
integrated semiconductor
circuit technology
semiconductor circuits
manufacturing integrated
universal circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68928308T
Other languages
English (en)
Other versions
DE68928308T2 (de
Inventor
Ryoichi Ohe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE68928308D1 publication Critical patent/DE68928308D1/de
Publication of DE68928308T2 publication Critical patent/DE68928308T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/909—Macrocell arrays, e.g. gate arrays with variable size or configuration of cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
DE68928308T 1988-06-16 1989-06-16 Verfahren zum Herstellen von integrierten Halbleiterschaltungen in der Universalschaltkreistechnik Expired - Fee Related DE68928308T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63146865A JP2666807B2 (ja) 1988-06-16 1988-06-16 集積回路パターンの形成方法

Publications (2)

Publication Number Publication Date
DE68928308D1 true DE68928308D1 (de) 1997-10-16
DE68928308T2 DE68928308T2 (de) 1998-01-08

Family

ID=15417316

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68928308T Expired - Fee Related DE68928308T2 (de) 1988-06-16 1989-06-16 Verfahren zum Herstellen von integrierten Halbleiterschaltungen in der Universalschaltkreistechnik

Country Status (5)

Country Link
US (1) US5081059A (de)
EP (1) EP0347332B1 (de)
JP (1) JP2666807B2 (de)
KR (1) KR920004225B1 (de)
DE (1) DE68928308T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5037771A (en) * 1989-11-28 1991-08-06 Cross-Check Technology, Inc. Method for implementing grid-based crosscheck test structures and the structures resulting therefrom
WO1993012582A1 (en) * 1991-12-13 1993-06-24 Knights Technology, Inc. Programmable logic device cell and method
US5618744A (en) * 1992-09-22 1997-04-08 Fujitsu Ltd. Manufacturing method and apparatus of a semiconductor integrated circuit device
WO1995002903A1 (en) * 1993-07-15 1995-01-26 Astarix, Inc. Contact programmable wiring and cell array architecture
TW591761B (en) * 2003-07-11 2004-06-11 Macronix Int Co Ltd NAND type binary nitride read only memory and the manufacturing method
EP2079109A3 (de) * 2004-11-05 2010-06-30 Fujitsu Semiconductor Limited Verfahren zum Entwurf eines integrierten Halbleiterschaltkreises
WO2006076151A2 (en) * 2004-12-21 2006-07-20 Carnegie Mellon University Lithography and associated methods, devices, and systems

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2524206B1 (fr) * 1982-03-26 1985-12-13 Thomson Csf Mat Tel Circuit integre prediffuse, et procede d'interconnexion des cellules de ce circuit
JPS5969948A (ja) * 1982-10-15 1984-04-20 Fujitsu Ltd マスタ−スライス型半導体集積回路
EP0127100B1 (de) * 1983-05-24 1990-04-11 Kabushiki Kaisha Toshiba Integrierte Halbleiterschaltungsanordnung
JPS6047441A (ja) * 1983-08-26 1985-03-14 Fujitsu Ltd 半導体集積回路
US4649413A (en) * 1983-08-29 1987-03-10 Texas Instruments Incorporated MOS integrated circuit having a metal programmable matrix
JPS6065547A (ja) * 1983-09-20 1985-04-15 Sharp Corp 半導体装置
JPS60144956A (ja) * 1984-01-06 1985-07-31 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPS6218732A (ja) * 1985-07-15 1987-01-27 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 集積回路とその個性化方法
JPS6235537A (ja) * 1985-08-08 1987-02-16 Nec Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
EP0347332A2 (de) 1989-12-20
KR900001005A (ko) 1990-01-31
EP0347332A3 (de) 1992-09-09
DE68928308T2 (de) 1998-01-08
KR920004225B1 (ko) 1992-05-30
EP0347332B1 (de) 1997-09-10
JP2666807B2 (ja) 1997-10-22
JPH022674A (ja) 1990-01-08
US5081059A (en) 1992-01-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee