DE68923730D1 - Verfahren zur Herstellung einer bipolaren integrierten Schaltung. - Google Patents
Verfahren zur Herstellung einer bipolaren integrierten Schaltung.Info
- Publication number
- DE68923730D1 DE68923730D1 DE68923730T DE68923730T DE68923730D1 DE 68923730 D1 DE68923730 D1 DE 68923730D1 DE 68923730 T DE68923730 T DE 68923730T DE 68923730 T DE68923730 T DE 68923730T DE 68923730 D1 DE68923730 D1 DE 68923730D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing
- integrated circuit
- bipolar integrated
- bipolar
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/011—Bipolar transistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/037—Diffusion-deposition
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/191,461 US4902633A (en) | 1988-05-09 | 1988-05-09 | Process for making a bipolar integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68923730D1 true DE68923730D1 (de) | 1995-09-14 |
DE68923730T2 DE68923730T2 (de) | 1996-04-04 |
Family
ID=22705591
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE68923730T Expired - Fee Related DE68923730T2 (de) | 1988-05-09 | 1989-04-20 | Verfahren zur Herstellung einer bipolaren integrierten Schaltung. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4902633A (de) |
EP (1) | EP0341461B1 (de) |
JP (1) | JP2700487B2 (de) |
DE (1) | DE68923730T2 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06101540B2 (ja) * | 1989-05-19 | 1994-12-12 | 三洋電機株式会社 | 半導体集積回路の製造方法 |
US5139961A (en) * | 1990-04-02 | 1992-08-18 | National Semiconductor Corporation | Reducing base resistance of a bjt by forming a self aligned silicide in the single crystal region of the extrinsic base |
US5200347A (en) * | 1991-02-14 | 1993-04-06 | Linear Technology Corporation | Method for improving the radiation hardness of an integrated circuit bipolar transistor |
US6043555A (en) * | 1995-04-13 | 2000-03-28 | Telefonaktiebolget Lm Ericsson | Bipolar silicon-on-insulator transistor with increased breakdown voltage |
SE515867C2 (sv) * | 1995-04-13 | 2001-10-22 | Ericsson Telefon Ab L M | Bipolär SOI-transistor |
US5702959A (en) * | 1995-05-31 | 1997-12-30 | Texas Instruments Incorporated | Method for making an isolated vertical transistor |
TW200733244A (en) * | 2005-10-06 | 2007-09-01 | Nxp Bv | Semiconductor device |
JP2007158188A (ja) * | 2005-12-07 | 2007-06-21 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP2007165370A (ja) * | 2005-12-09 | 2007-06-28 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP5261640B2 (ja) * | 2005-12-09 | 2013-08-14 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 半導体装置の製造方法 |
FR2978614B1 (fr) * | 2011-07-25 | 2014-09-05 | Altis Semiconductor Snc | Substrat semi-conducteur comprenant des zones dopees formant une jonction p-n |
CN102664161B (zh) | 2012-05-25 | 2016-11-16 | 杭州士兰集成电路有限公司 | 高压bcd工艺中高压器件的隔离结构及其制造方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US30282A (en) * | 1860-10-09 | Quartz crusher and amalgamator | ||
US3473977A (en) * | 1967-02-02 | 1969-10-21 | Westinghouse Electric Corp | Semiconductor fabrication technique permitting examination of epitaxially grown layers |
US3544863A (en) * | 1968-10-29 | 1970-12-01 | Motorola Inc | Monolithic integrated circuit substructure with epitaxial decoupling capacitance |
FR2041710B1 (de) * | 1969-05-08 | 1974-06-14 | Radiotechnique Compelec | |
DE2031831A1 (de) * | 1969-06-27 | 1972-03-02 | Hitachi Ltd | Halbleiterdiode und Verfahren zu ihrer Herstellung |
US3622842A (en) * | 1969-12-29 | 1971-11-23 | Ibm | Semiconductor device having high-switching speed and method of making |
US3982974A (en) * | 1971-11-22 | 1976-09-28 | International Business Machines Corporation | Compensation of autodoping in the manufacture of integrated circuits |
JPS5942463B2 (ja) * | 1972-09-22 | 1984-10-15 | ソニー株式会社 | 半導体集積回路装置 |
USRE30282E (en) * | 1976-06-28 | 1980-05-27 | Motorola, Inc. | Double master mask process for integrated circuit manufacture |
US4111720A (en) * | 1977-03-31 | 1978-09-05 | International Business Machines Corporation | Method for forming a non-epitaxial bipolar integrated circuit |
IT1101096B (it) * | 1978-12-22 | 1985-09-28 | Ates Componenti Elettron | Perfezionamento al procedimento per produrre dispositivi integrati a semiconduttore e prodotto risultante |
DE3136364A1 (de) * | 1980-12-05 | 1982-11-18 | VEB Halbleiterwerk Frankfurt/Oder Leitbetrieb im VEB Kombinat Mikroelektronik, DDR 1200 Frankfurt | Verfahren zur herstellung integrierter schaltkreise |
JPS58210659A (ja) * | 1982-06-01 | 1983-12-07 | Nec Corp | 半導体装置およびその製造方法 |
US4593457A (en) * | 1984-12-17 | 1986-06-10 | Motorola, Inc. | Method for making gallium arsenide NPN transistor with self-aligned base enhancement to emitter region and metal contact |
US4717681A (en) * | 1986-05-19 | 1988-01-05 | Texas Instruments Incorporated | Method of making a heterojunction bipolar transistor with SIPOS |
JPS6318673A (ja) * | 1986-07-11 | 1988-01-26 | Yamaha Corp | 半導体装置の製法 |
IT1215024B (it) * | 1986-10-01 | 1990-01-31 | Sgs Microelettronica Spa | Processo per la formazione di un dispositivo monolitico a semiconduttore di alta tensione |
-
1988
- 1988-05-09 US US07/191,461 patent/US4902633A/en not_active Expired - Lifetime
-
1989
- 1989-04-19 JP JP1099914A patent/JP2700487B2/ja not_active Expired - Fee Related
- 1989-04-20 EP EP89107083A patent/EP0341461B1/de not_active Expired - Lifetime
- 1989-04-20 DE DE68923730T patent/DE68923730T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US4902633A (en) | 1990-02-20 |
EP0341461A2 (de) | 1989-11-15 |
EP0341461A3 (en) | 1990-05-16 |
EP0341461B1 (de) | 1995-08-09 |
DE68923730T2 (de) | 1996-04-04 |
JPH0217646A (ja) | 1990-01-22 |
JP2700487B2 (ja) | 1998-01-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8320 | Willingness to grant licences declared (paragraph 23) | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: FREESCALE SEMICONDUCTOR, INC. (N.D.GES.D. STAATES |
|
8339 | Ceased/non-payment of the annual fee |