EP0341461A3 - Process for making a bipolar integrated circuit - Google Patents
Process for making a bipolar integrated circuit Download PDFInfo
- Publication number
- EP0341461A3 EP0341461A3 EP89107083A EP89107083A EP0341461A3 EP 0341461 A3 EP0341461 A3 EP 0341461A3 EP 89107083 A EP89107083 A EP 89107083A EP 89107083 A EP89107083 A EP 89107083A EP 0341461 A3 EP0341461 A3 EP 0341461A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- making
- integrated circuit
- bipolar integrated
- bipolar
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/011—Bipolar transistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/037—Diffusion-deposition
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Bipolar Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US191461 | 1988-05-09 | ||
US07/191,461 US4902633A (en) | 1988-05-09 | 1988-05-09 | Process for making a bipolar integrated circuit |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0341461A2 EP0341461A2 (en) | 1989-11-15 |
EP0341461A3 true EP0341461A3 (en) | 1990-05-16 |
EP0341461B1 EP0341461B1 (en) | 1995-08-09 |
Family
ID=22705591
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP89107083A Expired - Lifetime EP0341461B1 (en) | 1988-05-09 | 1989-04-20 | Process for making a bipolar integrated circuit |
Country Status (4)
Country | Link |
---|---|
US (1) | US4902633A (en) |
EP (1) | EP0341461B1 (en) |
JP (1) | JP2700487B2 (en) |
DE (1) | DE68923730T2 (en) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06101540B2 (en) * | 1989-05-19 | 1994-12-12 | 三洋電機株式会社 | Method for manufacturing semiconductor integrated circuit |
US5139961A (en) * | 1990-04-02 | 1992-08-18 | National Semiconductor Corporation | Reducing base resistance of a bjt by forming a self aligned silicide in the single crystal region of the extrinsic base |
US5200347A (en) * | 1991-02-14 | 1993-04-06 | Linear Technology Corporation | Method for improving the radiation hardness of an integrated circuit bipolar transistor |
US6043555A (en) * | 1995-04-13 | 2000-03-28 | Telefonaktiebolget Lm Ericsson | Bipolar silicon-on-insulator transistor with increased breakdown voltage |
SE515867C2 (en) * | 1995-04-13 | 2001-10-22 | Ericsson Telefon Ab L M | Bipolar SOI transistor |
US5702959A (en) * | 1995-05-31 | 1997-12-30 | Texas Instruments Incorporated | Method for making an isolated vertical transistor |
TW200733244A (en) * | 2005-10-06 | 2007-09-01 | Nxp Bv | Semiconductor device |
JP2007158188A (en) * | 2005-12-07 | 2007-06-21 | Sanyo Electric Co Ltd | Semiconductor device, and method of manufacturing same |
JP2007165370A (en) * | 2005-12-09 | 2007-06-28 | Sanyo Electric Co Ltd | Semiconductor device, and method of manufacturing same |
JP5261640B2 (en) * | 2005-12-09 | 2013-08-14 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Manufacturing method of semiconductor device |
FR2978614B1 (en) * | 2011-07-25 | 2014-09-05 | Altis Semiconductor Snc | SEMICONDUCTOR SUBSTRATE COMPRISING DOPED AREAS FORMING A P-N JUNCTION |
CN102664161B (en) | 2012-05-25 | 2016-11-16 | 杭州士兰集成电路有限公司 | The isolation structure of High voltage BCD process mesohigh device and manufacture method thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3982974A (en) * | 1971-11-22 | 1976-09-28 | International Business Machines Corporation | Compensation of autodoping in the manufacture of integrated circuits |
USRE30282E (en) * | 1976-06-28 | 1980-05-27 | Motorola, Inc. | Double master mask process for integrated circuit manufacture |
FR2445022A1 (en) * | 1978-12-22 | 1980-07-18 | Ates Componenti Elettron | IMPROVEMENT RELATING TO THE PROCESS FOR THE PRODUCTION OF INTEGRATED SEMICONDUCTOR DEVICES AND THE PRODUCT THUS OBTAINED |
DE3136364A1 (en) * | 1980-12-05 | 1982-11-18 | VEB Halbleiterwerk Frankfurt/Oder Leitbetrieb im VEB Kombinat Mikroelektronik, DDR 1200 Frankfurt | Method for manufacturing integrated circuits |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US30282A (en) * | 1860-10-09 | Quartz crusher and amalgamator | ||
US3473977A (en) * | 1967-02-02 | 1969-10-21 | Westinghouse Electric Corp | Semiconductor fabrication technique permitting examination of epitaxially grown layers |
US3544863A (en) * | 1968-10-29 | 1970-12-01 | Motorola Inc | Monolithic integrated circuit substructure with epitaxial decoupling capacitance |
FR2041710B1 (en) * | 1969-05-08 | 1974-06-14 | Radiotechnique Compelec | |
DE2031831A1 (en) * | 1969-06-27 | 1972-03-02 | Hitachi Ltd | Semiconductor diode and process for its manufacture |
US3622842A (en) * | 1969-12-29 | 1971-11-23 | Ibm | Semiconductor device having high-switching speed and method of making |
JPS5942463B2 (en) * | 1972-09-22 | 1984-10-15 | ソニー株式会社 | Semiconductor integrated circuit device |
US4111720A (en) * | 1977-03-31 | 1978-09-05 | International Business Machines Corporation | Method for forming a non-epitaxial bipolar integrated circuit |
JPS58210659A (en) * | 1982-06-01 | 1983-12-07 | Nec Corp | Semiconductor device and manufacture thereof |
US4593457A (en) * | 1984-12-17 | 1986-06-10 | Motorola, Inc. | Method for making gallium arsenide NPN transistor with self-aligned base enhancement to emitter region and metal contact |
US4717681A (en) * | 1986-05-19 | 1988-01-05 | Texas Instruments Incorporated | Method of making a heterojunction bipolar transistor with SIPOS |
JPS6318673A (en) * | 1986-07-11 | 1988-01-26 | Yamaha Corp | Manufacture of semiconductor device |
IT1215024B (en) * | 1986-10-01 | 1990-01-31 | Sgs Microelettronica Spa | PROCESS FOR THE FORMATION OF A HIGH VOLTAGE SEMICONDUCTOR MONOLITHIC DEVICE |
-
1988
- 1988-05-09 US US07/191,461 patent/US4902633A/en not_active Expired - Lifetime
-
1989
- 1989-04-19 JP JP1099914A patent/JP2700487B2/en not_active Expired - Fee Related
- 1989-04-20 EP EP89107083A patent/EP0341461B1/en not_active Expired - Lifetime
- 1989-04-20 DE DE68923730T patent/DE68923730T2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3982974A (en) * | 1971-11-22 | 1976-09-28 | International Business Machines Corporation | Compensation of autodoping in the manufacture of integrated circuits |
USRE30282E (en) * | 1976-06-28 | 1980-05-27 | Motorola, Inc. | Double master mask process for integrated circuit manufacture |
FR2445022A1 (en) * | 1978-12-22 | 1980-07-18 | Ates Componenti Elettron | IMPROVEMENT RELATING TO THE PROCESS FOR THE PRODUCTION OF INTEGRATED SEMICONDUCTOR DEVICES AND THE PRODUCT THUS OBTAINED |
DE3136364A1 (en) * | 1980-12-05 | 1982-11-18 | VEB Halbleiterwerk Frankfurt/Oder Leitbetrieb im VEB Kombinat Mikroelektronik, DDR 1200 Frankfurt | Method for manufacturing integrated circuits |
Non-Patent Citations (1)
Title |
---|
FROM ELECTRONICS TO MICROELECTRONICS; FOURTH EUROPEAN CONFERENCE ON ELECTRONICS - EUROCON '80, 1980, pages 745-749; M. DEPEY: "Compatibility of high voltage analog functions and I2L digital functions" * |
Also Published As
Publication number | Publication date |
---|---|
DE68923730T2 (en) | 1996-04-04 |
EP0341461B1 (en) | 1995-08-09 |
US4902633A (en) | 1990-02-20 |
DE68923730D1 (en) | 1995-09-14 |
JPH0217646A (en) | 1990-01-22 |
EP0341461A2 (en) | 1989-11-15 |
JP2700487B2 (en) | 1998-01-21 |
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