DE68915395D1 - Dynamische Speicheranordnung mit verbessertem Leitungsnetz. - Google Patents

Dynamische Speicheranordnung mit verbessertem Leitungsnetz.

Info

Publication number
DE68915395D1
DE68915395D1 DE68915395T DE68915395T DE68915395D1 DE 68915395 D1 DE68915395 D1 DE 68915395D1 DE 68915395 T DE68915395 T DE 68915395T DE 68915395 T DE68915395 T DE 68915395T DE 68915395 D1 DE68915395 D1 DE 68915395D1
Authority
DE
Germany
Prior art keywords
storage arrangement
dynamic storage
pipeline network
improved pipeline
improved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68915395T
Other languages
English (en)
Other versions
DE68915395T2 (de
Inventor
Jumpei C O Intellectua Kumagai
Syuso C O Intellectual P Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE68915395D1 publication Critical patent/DE68915395D1/de
Application granted granted Critical
Publication of DE68915395T2 publication Critical patent/DE68915395T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/922—Active solid-state devices, e.g. transistors, solid-state diodes with means to prevent inspection of or tampering with an integrated circuit, e.g. "smart card", anti-tamper
DE68915395T 1988-11-16 1989-10-19 Dynamische Speicheranordnung mit verbessertem Leitungsnetz. Expired - Fee Related DE68915395T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63289259A JPH07109878B2 (ja) 1988-11-16 1988-11-16 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE68915395D1 true DE68915395D1 (de) 1994-06-23
DE68915395T2 DE68915395T2 (de) 1994-10-06

Family

ID=17740841

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68915395T Expired - Fee Related DE68915395T2 (de) 1988-11-16 1989-10-19 Dynamische Speicheranordnung mit verbessertem Leitungsnetz.

Country Status (5)

Country Link
US (1) US4941031A (de)
EP (1) EP0369183B1 (de)
JP (1) JPH07109878B2 (de)
KR (1) KR930000766B1 (de)
DE (1) DE68915395T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5194752A (en) * 1989-05-23 1993-03-16 Kabushiki Kaisha Toshiba Semiconductor memory device
JP2953708B2 (ja) * 1989-07-31 1999-09-27 株式会社東芝 ダイナミック型半導体記憶装置
JPH0713864B2 (ja) * 1989-09-27 1995-02-15 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
EP0496406B1 (de) * 1991-01-25 1999-05-06 Nec Corporation Halbleiterspeicheranordnung
JPH0669208A (ja) * 1991-03-12 1994-03-11 Oki Electric Ind Co Ltd 半導体装置
US5639690A (en) * 1991-03-12 1997-06-17 Oki Electric Industry Co., Ltd. Method for manufacturing a conductive pattern structure for a semiconductor device
US5170243A (en) * 1991-11-04 1992-12-08 International Business Machines Corporation Bit line configuration for semiconductor memory
EP0713251B1 (de) * 1992-11-18 1999-01-07 Fuji Electric Co. Ltd. Halbleiter-Umwandlungsvorrichtung
KR100298871B1 (ko) * 1993-06-02 2001-11-22 김영환 반도체 메모리 장치의 비트라인 구조
US5485419A (en) * 1994-05-23 1996-01-16 Campbell; John P. Memory device column address selection lead layout
US5670815A (en) * 1994-07-05 1997-09-23 Motorola, Inc. Layout for noise reduction on a reference voltage
US5636158A (en) * 1995-03-13 1997-06-03 Kabushiki Kaisha Toshiba Irregular pitch layout for a semiconductor memory device
US5899706A (en) * 1997-06-30 1999-05-04 Siemens Aktiengesellschaft Method of reducing loading variation during etch processing
JP2000216264A (ja) 1999-01-22 2000-08-04 Mitsubishi Electric Corp Ｃｍｏｓ論理回路素子、半導体装置とその製造方法およびその製造方法において用いる半導体回路設計方法
JP2002190532A (ja) * 2000-12-19 2002-07-05 Hitachi Ltd 半導体記憶装置
JP2008004889A (ja) * 2006-06-26 2008-01-10 Samsung Electronics Co Ltd 半導体記憶装置
JP2008227171A (ja) * 2007-03-13 2008-09-25 Toshiba Corp 不揮発性半導体メモリ
US7948094B2 (en) * 2007-10-22 2011-05-24 Rohm Co., Ltd. Semiconductor device
KR102635666B1 (ko) * 2018-08-16 2024-02-14 에스케이하이닉스 주식회사 반도체 메모리 장치

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5349969A (en) * 1976-10-18 1978-05-06 Hitachi Ltd Semiconductor memory unit
US4319342A (en) * 1979-12-26 1982-03-09 International Business Machines Corporation One device field effect transistor (FET) AC stable random access memory (RAM) array
JPS5772348A (en) * 1980-10-24 1982-05-06 Nec Corp Wiring structure in integrated circuit
JPS59231852A (ja) * 1983-06-15 1984-12-26 Hitachi Ltd 半導体装置
JPH0714006B2 (ja) * 1985-05-29 1995-02-15 株式会社東芝 ダイナミツク型メモリ
JPS6211262A (ja) * 1985-07-08 1987-01-20 Nec Ic Microcomput Syst Ltd 半導体記憶装置
JPS6265300A (ja) * 1985-09-18 1987-03-24 Toshiba Corp 半導体記憶装置
JPS6276761A (ja) * 1985-09-30 1987-04-08 Toshiba Corp 半導体装置
JPH0766659B2 (ja) * 1986-01-30 1995-07-19 三菱電機株式会社 半導体記憶装置
JPS6367771A (ja) * 1986-09-09 1988-03-26 Mitsubishi Electric Corp 半導体記憶装置
JPS63183691A (ja) * 1987-01-26 1988-07-29 Mitsubishi Electric Corp 半導体記憶装置

Also Published As

Publication number Publication date
US4941031A (en) 1990-07-10
EP0369183A3 (de) 1991-01-23
JPH02134868A (ja) 1990-05-23
JPH07109878B2 (ja) 1995-11-22
EP0369183B1 (de) 1994-05-18
KR930000766B1 (ko) 1993-02-01
DE68915395T2 (de) 1994-10-06
KR900008521A (ko) 1990-06-03
EP0369183A2 (de) 1990-05-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee