DE68908650D1 - Dynamisch wahlfreie Speichereinrichtung. - Google Patents

Dynamisch wahlfreie Speichereinrichtung.

Info

Publication number
DE68908650D1
DE68908650D1 DE89309472T DE68908650T DE68908650D1 DE 68908650 D1 DE68908650 D1 DE 68908650D1 DE 89309472 T DE89309472 T DE 89309472T DE 68908650 T DE68908650 T DE 68908650T DE 68908650 D1 DE68908650 D1 DE 68908650D1
Authority
DE
Germany
Prior art keywords
storage facility
random storage
dynamically random
dynamically
facility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE89309472T
Other languages
English (en)
Other versions
DE68908650T2 (de
Inventor
Taiji Ema
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE68908650D1 publication Critical patent/DE68908650D1/de
Publication of DE68908650T2 publication Critical patent/DE68908650T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
DE89309472T 1988-09-19 1989-09-19 Dynamisch wahlfreie Speichereinrichtung. Expired - Fee Related DE68908650T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63232232A JP2681285B2 (ja) 1988-09-19 1988-09-19 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE68908650D1 true DE68908650D1 (de) 1993-09-30
DE68908650T2 DE68908650T2 (de) 1993-12-23

Family

ID=16936045

Family Applications (1)

Application Number Title Priority Date Filing Date
DE89309472T Expired - Fee Related DE68908650T2 (de) 1988-09-19 1989-09-19 Dynamisch wahlfreie Speichereinrichtung.

Country Status (5)

Country Link
US (1) US5396451A (de)
EP (1) EP0360541B1 (de)
JP (1) JP2681285B2 (de)
KR (1) KR930007835B1 (de)
DE (1) DE68908650T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920007358B1 (ko) * 1990-03-28 1992-08-31 금성일렉트론 주식회사 고집적 메모리 셀 및 코아 어레이 구조
JP3101297B2 (ja) * 1990-03-30 2000-10-23 株式会社東芝 半導体メモリ装置
US5864181A (en) 1993-09-15 1999-01-26 Micron Technology, Inc. Bi-level digit line architecture for high density DRAMs
JP2638487B2 (ja) * 1994-06-30 1997-08-06 日本電気株式会社 半導体記憶装置
TW318281B (de) * 1994-08-30 1997-10-21 Mitsubishi Electric Corp
US5546349A (en) * 1995-03-13 1996-08-13 Kabushiki Kaisha Toshiba Exchangeable hierarchical data line structure
KR0161474B1 (ko) * 1995-12-15 1999-02-01 김광호 셀 플러그 이온주입을 이용한 반도체 메모리장치의 제조방법
US6043562A (en) 1996-01-26 2000-03-28 Micron Technology, Inc. Digit line architecture for dynamic memory
KR100236067B1 (ko) * 1996-09-02 1999-12-15 김영환 반도체 메모리 소자 제조방법
US5864496A (en) * 1997-09-29 1999-01-26 Siemens Aktiengesellschaft High density semiconductor memory having diagonal bit lines and dual word lines
US6249451B1 (en) 1999-02-08 2001-06-19 Kabushiki Kaisha Toshiba Data line connections with twisting scheme technical field
DE10241171A1 (de) * 2002-09-05 2004-03-18 Infineon Technologies Ag Wort- und Bitleitungsanordnung für einen FINFET-Halbleiterspeicher
DE102004059723B4 (de) * 2004-12-11 2010-02-25 Qimonda Ag Speicherbauelement mit neuer Anordnung der Bitleitungen
US7773412B2 (en) * 2006-05-22 2010-08-10 Micron Technology, Inc. Method and apparatus for providing a non-volatile memory with reduced cell capacitive coupling
US7589019B2 (en) 2006-05-31 2009-09-15 Infineon Technologies, Ag Memory cell array and method of forming a memory cell array
US7817454B2 (en) * 2007-04-03 2010-10-19 Micron Technology, Inc. Variable resistance memory with lattice array using enclosing transistors
CN103187090A (zh) * 2013-03-19 2013-07-03 西安华芯半导体有限公司 一种存储阵列及存储器
CN110176265B (zh) * 2019-04-29 2021-06-04 长江存储科技有限责任公司 多层存储器及其制作方法
CN114078853B (zh) * 2020-08-18 2023-02-24 长鑫存储技术有限公司 存储器及其制作方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4319342A (en) * 1979-12-26 1982-03-09 International Business Machines Corporation One device field effect transistor (FET) AC stable random access memory (RAM) array
US4649406A (en) * 1982-12-20 1987-03-10 Fujitsu Limited Semiconductor memory device having stacked capacitor-type memory cells
JPS602784B2 (ja) * 1982-12-20 1985-01-23 富士通株式会社 半導体記憶装置
US4651183A (en) * 1984-06-28 1987-03-17 International Business Machines Corporation High density one device memory cell arrays
JPH0760858B2 (ja) * 1984-10-26 1995-06-28 三菱電機株式会社 半導体メモリ装置
JPS61183952A (ja) * 1985-02-09 1986-08-16 Fujitsu Ltd 半導体記憶装置及びその製造方法
JPH0736437B2 (ja) * 1985-11-29 1995-04-19 株式会社日立製作所 半導体メモリの製造方法
JPS62200596A (ja) * 1986-02-26 1987-09-04 Mitsubishi Electric Corp 半導体メモリ
JPS6386186A (ja) * 1986-09-30 1988-04-16 Toshiba Corp 半導体記憶装置
DE3856143T2 (de) * 1987-06-17 1998-10-29 Fujitsu Ltd Verfahren zum Herstellen einer dynamischen Speicherzelle mit wahlfreiem Zugriff
JPH073860B2 (ja) * 1987-06-17 1995-01-18 富士通株式会社 半導体記憶装置の製造方法
JP2642364B2 (ja) * 1987-12-03 1997-08-20 富士通株式会社 半導体記憶装置及びその製造方法
US5071783A (en) * 1987-06-17 1991-12-10 Fujitsu Limited Method of producing a dynamic random access memory device
JP2627515B2 (ja) * 1987-12-10 1997-07-09 富士通株式会社 半導体記憶装置及びその製造方法
JPS6413290A (en) * 1987-07-07 1989-01-18 Oki Electric Ind Co Ltd Semiconductor memory

Also Published As

Publication number Publication date
JP2681285B2 (ja) 1997-11-26
EP0360541A1 (de) 1990-03-28
DE68908650T2 (de) 1993-12-23
JPH0281473A (ja) 1990-03-22
KR900005465A (ko) 1990-04-14
KR930007835B1 (en) 1993-08-20
EP0360541B1 (de) 1993-08-25
US5396451A (en) 1995-03-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee