DE60224727D1 - Multimodus-synchronspeichervorrichtung und verfahren zum betrieb und testen derselben - Google Patents

Multimodus-synchronspeichervorrichtung und verfahren zum betrieb und testen derselben

Info

Publication number
DE60224727D1
DE60224727D1 DE60224727T DE60224727T DE60224727D1 DE 60224727 D1 DE60224727 D1 DE 60224727D1 DE 60224727 T DE60224727 T DE 60224727T DE 60224727 T DE60224727 T DE 60224727T DE 60224727 D1 DE60224727 D1 DE 60224727D1
Authority
DE
Germany
Prior art keywords
clock signal
mode
external clock
responsive
asynchronous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60224727T
Other languages
English (en)
Other versions
DE60224727T2 (de
Inventor
Brian Johnson
Brent Keeth
Jeffrey W Janzen
Troy A Manning
Chris G Martin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE60224727D1 publication Critical patent/DE60224727D1/de
Application granted granted Critical
Publication of DE60224727T2 publication Critical patent/DE60224727T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
DE60224727T 2001-12-26 2002-12-18 Multimodus-synchronspeichervorrichtung und verfahren zum betrieb und testen derselben Expired - Lifetime DE60224727T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US36141 2001-12-26
US10/036,141 US6678205B2 (en) 2001-12-26 2001-12-26 Multi-mode synchronous memory device and method of operating and testing same
PCT/US2002/040447 WO2003058630A1 (en) 2001-12-26 2002-12-18 Multi-mode synchronous memory device and method of operating and testing same

Publications (2)

Publication Number Publication Date
DE60224727D1 true DE60224727D1 (de) 2008-03-06
DE60224727T2 DE60224727T2 (de) 2009-01-15

Family

ID=21886877

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60224727T Expired - Lifetime DE60224727T2 (de) 2001-12-26 2002-12-18 Multimodus-synchronspeichervorrichtung und verfahren zum betrieb und testen derselben

Country Status (10)

Country Link
US (3) US6678205B2 (de)
EP (1) EP1459323B1 (de)
JP (1) JP2005514721A (de)
KR (1) KR100592648B1 (de)
CN (1) CN100424781C (de)
AT (1) ATE384328T1 (de)
AU (1) AU2002361761A1 (de)
DE (1) DE60224727T2 (de)
TW (1) TWI222068B (de)
WO (1) WO2003058630A1 (de)

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ITRM20010556A1 (it) * 2001-09-12 2003-03-12 Micron Technology Inc Decodificatore per decodificare i comandi di commutazione a modo di test di circuiti integrati.
US6678205B2 (en) * 2001-12-26 2004-01-13 Micron Technology, Inc. Multi-mode synchronous memory device and method of operating and testing same
US7142461B2 (en) * 2002-11-20 2006-11-28 Micron Technology, Inc. Active termination control though on module register
DE10305837B4 (de) * 2003-02-12 2009-03-19 Qimonda Ag Speichermodul mit einer Mehrzahl von integrierten Speicherbauelementen
JP4327482B2 (ja) * 2003-03-18 2009-09-09 富士通マイクロエレクトロニクス株式会社 同期型半導体記憶装置
KR100522433B1 (ko) 2003-04-29 2005-10-20 주식회사 하이닉스반도체 도메인 크로싱 회로
US6961269B2 (en) * 2003-06-24 2005-11-01 Micron Technology, Inc. Memory device having data paths with multiple speeds
KR100543925B1 (ko) * 2003-06-27 2006-01-23 주식회사 하이닉스반도체 지연 고정 루프 및 지연 고정 루프에서의 클럭 지연 고정방법
JP2005049970A (ja) * 2003-07-30 2005-02-24 Renesas Technology Corp 半導体集積回路
US20070257716A1 (en) * 2004-03-05 2007-11-08 Mohamed Azimane Dft Technique for Stressing Self-Timed Semiconductor Memories to Detect Delay Faults
KR100612952B1 (ko) 2004-04-30 2006-08-14 주식회사 하이닉스반도체 전력소모를 줄인 동기식 반도체메모리소자
US7519877B2 (en) 2004-08-10 2009-04-14 Micron Technology, Inc. Memory with test mode output
US7536570B2 (en) * 2006-10-02 2009-05-19 Silicon Laboratories Inc. Microcontroller unit (MCU) with suspend mode
WO2008041974A2 (en) * 2006-10-02 2008-04-10 Kafai Leung Microcontroller unit (mcu) with suspend mode
WO2008075311A2 (en) 2006-12-20 2008-06-26 Nxp B.V. Clock generation for memory access without a local oscillator
US7685542B2 (en) * 2007-02-09 2010-03-23 International Business Machines Corporation Method and apparatus for shutting off data capture across asynchronous clock domains during at-speed testing
JP2008217947A (ja) * 2007-03-07 2008-09-18 Elpida Memory Inc 半導体記憶装置
US7779375B2 (en) * 2007-10-17 2010-08-17 International Business Machines Corporation Design structure for shutting off data capture across asynchronous clock domains during at-speed testing
US7936637B2 (en) * 2008-06-30 2011-05-03 Micron Technology, Inc. System and method for synchronizing asynchronous signals without external clock
KR101166800B1 (ko) 2010-05-28 2012-07-26 에스케이하이닉스 주식회사 지연회로
TWI460728B (zh) * 2010-12-29 2014-11-11 Silicon Motion Inc 記憶體控制器、記憶裝置以及判斷記憶裝置之型式的方法
US8522089B2 (en) * 2011-01-21 2013-08-27 Freescale Semiconductor, Inc. Method of testing asynchronous modules in semiconductor device
CN102081965B (zh) * 2011-02-21 2013-04-10 西安华芯半导体有限公司 一种产生dram内部写时钟的电路
CN102394633B (zh) * 2011-08-31 2013-08-21 华南理工大学 一种用于ldpc解码器的低功耗异步比较选通器
KR102291505B1 (ko) * 2014-11-24 2021-08-23 삼성전자주식회사 스토리지 장치 및 스토리지 장치의 동작 방법
CN105913868B (zh) * 2016-03-31 2018-09-21 华为技术有限公司 一种调整频率的方法、片上系统及终端
CN111381148B (zh) * 2018-12-29 2023-02-21 华润微集成电路(无锡)有限公司 实现芯片测试的系统及方法
CN113330685B (zh) * 2019-01-30 2023-10-20 华为技术有限公司 占空比调整方法、控制器芯片及闪存设备
CN109872744A (zh) * 2019-03-19 2019-06-11 济南德欧雅安全技术有限公司 一种方便测试的单元存储器
CN112088523B (zh) * 2019-03-27 2023-04-28 京东方科技集团股份有限公司 物联网系统、中央控制设备、应用设备以及通信方法
CN110843529B (zh) * 2019-10-10 2020-12-18 珠海格力电器股份有限公司 高压互锁故障自诊断电路、控制方法及新能源汽车
CN116203400B (zh) * 2023-04-27 2023-07-28 湖南大学 一种基于芯片初始化的测试方法及系统
CN116879725B (zh) * 2023-09-06 2023-12-08 西安紫光国芯半导体股份有限公司 一种采样电路、自测试电路以及芯片

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JP2001195899A (ja) * 2000-01-06 2001-07-19 Mitsubishi Electric Corp 半導体記憶装置
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KR100346835B1 (ko) * 2000-05-06 2002-08-03 삼성전자 주식회사 지연동기회로의 고속동작을 구현하는 반도체 메모리 장치
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Also Published As

Publication number Publication date
US7057967B2 (en) 2006-06-06
US20050094432A1 (en) 2005-05-05
AU2002361761A1 (en) 2003-07-24
US6678205B2 (en) 2004-01-13
CN100424781C (zh) 2008-10-08
US20030117881A1 (en) 2003-06-26
US6842398B2 (en) 2005-01-11
TW200301482A (en) 2003-07-01
KR20040074105A (ko) 2004-08-21
CN1620696A (zh) 2005-05-25
DE60224727T2 (de) 2009-01-15
EP1459323B1 (de) 2008-01-16
JP2005514721A (ja) 2005-05-19
TWI222068B (en) 2004-10-11
US20040090821A1 (en) 2004-05-13
ATE384328T1 (de) 2008-02-15
KR100592648B1 (ko) 2006-06-26
WO2003058630A1 (en) 2003-07-17
EP1459323A1 (de) 2004-09-22

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