DE60217977T2 - Halbleiterwafer und verfahren zu dessen herstellung - Google Patents

Halbleiterwafer und verfahren zu dessen herstellung Download PDF

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Publication number
DE60217977T2
DE60217977T2 DE60217977T DE60217977T DE60217977T2 DE 60217977 T2 DE60217977 T2 DE 60217977T2 DE 60217977 T DE60217977 T DE 60217977T DE 60217977 T DE60217977 T DE 60217977T DE 60217977 T2 DE60217977 T2 DE 60217977T2
Authority
DE
Germany
Prior art keywords
semiconductor wafer
wafer
mirror
semiconductor
polished part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60217977T
Other languages
German (de)
English (en)
Other versions
DE60217977D1 (de
Inventor
LTD. Hideki c/o NIKKO MATERIALS CO. Kitaibaraki-shi KURITA
LTD. Masashi c/o NIKKO MATERIALS CO. Toda-shi NAKAMURA
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Mining Holdings Inc
Original Assignee
Nippon Mining and Metals Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Mining and Metals Co Ltd filed Critical Nippon Mining and Metals Co Ltd
Publication of DE60217977D1 publication Critical patent/DE60217977D1/de
Application granted granted Critical
Publication of DE60217977T2 publication Critical patent/DE60217977T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12—Preparing bulk and homogeneous wafers
    • H10P90/128—Preparing bulk and homogeneous wafers by edge treatment, e.g. chamfering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2907—Materials being Group IIIA-VA materials
    • H10P14/2909—Phosphides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2924—Structures
    • H10P14/2925—Surface structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2926—Crystal orientations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3418—Phosphides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3421—Arsenides

Landscapes

  • Mechanical Treatment Of Semiconductor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
DE60217977T 2002-01-11 2002-12-17 Halbleiterwafer und verfahren zu dessen herstellung Expired - Lifetime DE60217977T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2002004124 2002-01-11
JP2002004124A JP4162892B2 (ja) 2002-01-11 2002-01-11 半導体ウェハおよびその製造方法
PCT/JP2002/013164 WO2003060965A1 (en) 2002-01-11 2002-12-17 Semiconductor wafer and method for producing the same

Publications (2)

Publication Number Publication Date
DE60217977D1 DE60217977D1 (de) 2007-03-22
DE60217977T2 true DE60217977T2 (de) 2007-05-24

Family

ID=19190960

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60217977T Expired - Lifetime DE60217977T2 (de) 2002-01-11 2002-12-17 Halbleiterwafer und verfahren zu dessen herstellung

Country Status (8)

Country Link
US (1) US6900522B2 (https=)
EP (1) EP1465242B1 (https=)
JP (1) JP4162892B2 (https=)
KR (1) KR100536932B1 (https=)
CN (1) CN1269185C (https=)
DE (1) DE60217977T2 (https=)
TW (1) TWI291724B (https=)
WO (1) WO2003060965A1 (https=)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3580311B1 (ja) * 2003-03-28 2004-10-20 住友電気工業株式会社 表裏識別した矩形窒化物半導体基板
US20050161808A1 (en) * 2004-01-22 2005-07-28 Anderson Douglas G. Wafer, intermediate wafer assembly and associated method for fabricating a silicon on insulator wafer having an improved edge profile
US8710665B2 (en) * 2008-10-06 2014-04-29 Infineon Technologies Ag Electronic component, a semiconductor wafer and a method for producing an electronic component
US20120028555A1 (en) * 2010-07-30 2012-02-02 Memc Electronic Materials, Inc. Grinding Tool For Trapezoid Grinding Of A Wafer
JP2013008769A (ja) * 2011-06-23 2013-01-10 Sumitomo Electric Ind Ltd 炭化珪素基板の製造方法
TWI473283B (zh) * 2011-09-21 2015-02-11 國立清華大學 晶片
JP6130995B2 (ja) * 2012-02-20 2017-05-17 サンケン電気株式会社 エピタキシャル基板及び半導体装置
JP2015018960A (ja) * 2013-07-11 2015-01-29 三菱電機株式会社 半導体装置の製造方法
JP6045542B2 (ja) * 2014-09-11 2016-12-14 信越半導体株式会社 半導体ウェーハの加工方法、貼り合わせウェーハの製造方法、及びエピタキシャルウェーハの製造方法
US10199216B2 (en) * 2015-12-24 2019-02-05 Infineon Technologies Austria Ag Semiconductor wafer and method
JP6750592B2 (ja) * 2017-08-15 2020-09-02 信越半導体株式会社 シリコンウエーハのエッジ形状の評価方法および評価装置、シリコンウエーハ、ならびにその選別方法および製造方法
JP7067465B2 (ja) * 2018-12-27 2022-05-16 株式会社Sumco 半導体ウェーハの評価方法及び半導体ウェーハの製造方法
JP7549322B2 (ja) * 2020-04-01 2024-09-11 株式会社ノベルクリスタルテクノロジー 半導体基板及びその製造方法
EP4170700A4 (en) * 2021-09-07 2024-01-03 JX Nippon Mining & Metals Corporation INDIUM PHOSPHIDE SUBSTRATE

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS504544B1 (https=) * 1970-12-21 1975-02-20
JPH0624179B2 (ja) * 1989-04-17 1994-03-30 信越半導体株式会社 半導体シリコンウェーハおよびその製造方法
JP2719855B2 (ja) * 1991-05-24 1998-02-25 信越半導体株式会社 ウエーハ外周の鏡面面取り装置
JP3027882B2 (ja) * 1992-07-31 2000-04-04 信越半導体株式会社 ウエーハ面取部研磨装置
JP2825048B2 (ja) * 1992-08-10 1998-11-18 信越半導体株式会社 半導体シリコン基板
JP2827885B2 (ja) * 1994-02-12 1998-11-25 信越半導体株式会社 半導体単結晶基板およびその製造方法
JPH09251934A (ja) * 1996-03-18 1997-09-22 Hitachi Ltd 半導体集積回路装置の製造方法および半導体ウエハ
JP3328193B2 (ja) * 1998-07-08 2002-09-24 信越半導体株式会社 半導体ウエーハの製造方法
JP3516203B2 (ja) * 1999-11-08 2004-04-05 株式会社日鉱マテリアルズ 化合物半導体ウェハ
JP4846915B2 (ja) * 2000-03-29 2011-12-28 信越半導体株式会社 貼り合わせウェーハの製造方法

Also Published As

Publication number Publication date
EP1465242A1 (en) 2004-10-06
JP2003209033A (ja) 2003-07-25
KR100536932B1 (ko) 2005-12-14
DE60217977D1 (de) 2007-03-22
CN1269185C (zh) 2006-08-09
US6900522B2 (en) 2005-05-31
TW200301931A (en) 2003-07-16
WO2003060965A1 (en) 2003-07-24
EP1465242B1 (en) 2007-01-31
US20040113236A1 (en) 2004-06-17
JP4162892B2 (ja) 2008-10-08
EP1465242A4 (en) 2005-08-17
CN1502117A (zh) 2004-06-02
TWI291724B (en) 2007-12-21
KR20040064612A (ko) 2004-07-19

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