DE69029596T2 - Halbleitendes Siliciumwafer und sein Herstellungsverfahren - Google Patents

Halbleitendes Siliciumwafer und sein Herstellungsverfahren

Info

Publication number
DE69029596T2
DE69029596T2 DE69029596T DE69029596T DE69029596T2 DE 69029596 T2 DE69029596 T2 DE 69029596T2 DE 69029596 T DE69029596 T DE 69029596T DE 69029596 T DE69029596 T DE 69029596T DE 69029596 T2 DE69029596 T2 DE 69029596T2
Authority
DE
Germany
Prior art keywords
manufacturing process
silicon wafer
semiconductor silicon
semiconductor
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69029596T
Other languages
English (en)
Other versions
DE69029596D1 (de
Inventor
Nobuyoshi Ogino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of DE69029596D1 publication Critical patent/DE69029596D1/de
Application granted granted Critical
Publication of DE69029596T2 publication Critical patent/DE69029596T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/161—Tapered edges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/21—Circular sheet or circular blank
    • Y10T428/219—Edge structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE69029596T 1989-04-17 1990-04-12 Halbleitendes Siliciumwafer und sein Herstellungsverfahren Expired - Fee Related DE69029596T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1097749A JPH0624179B2 (ja) 1989-04-17 1989-04-17 半導体シリコンウェーハおよびその製造方法

Publications (2)

Publication Number Publication Date
DE69029596D1 DE69029596D1 (de) 1997-02-20
DE69029596T2 true DE69029596T2 (de) 1997-07-10

Family

ID=14200535

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69029596T Expired - Fee Related DE69029596T2 (de) 1989-04-17 1990-04-12 Halbleitendes Siliciumwafer und sein Herstellungsverfahren

Country Status (4)

Country Link
US (2) US5021862A (de)
EP (1) EP0393951B1 (de)
JP (1) JPH0624179B2 (de)
DE (1) DE69029596T2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2628424B2 (ja) * 1992-01-24 1997-07-09 信越半導体株式会社 ウエーハ面取部の研磨方法及び装置
JP2827885B2 (ja) * 1994-02-12 1998-11-25 信越半導体株式会社 半導体単結晶基板およびその製造方法
JPH081493A (ja) * 1994-06-17 1996-01-09 Shin Etsu Handotai Co Ltd ウェーハ面取部の鏡面研磨方法および鏡面研磨装置
JP3379097B2 (ja) * 1995-11-27 2003-02-17 信越半導体株式会社 両面研磨装置及び方法
DE19707887C2 (de) * 1997-02-27 2002-07-11 Micronas Semiconductor Holding Verfahren zum Herstellen und Trennen von elektronischen Elementen mit leitfähigen Kontaktanschlüssen
FR2770685B1 (fr) * 1997-10-31 2000-01-14 Sgs Thomson Microelectronics Procede d'amincissement d'une plaquette de semiconducteur
US6454514B2 (en) * 1998-07-08 2002-09-24 Semitool, Inc. Microelectronic workpiece support and apparatus using the support
DE10131246C2 (de) * 2001-06-28 2002-12-19 Wacker Siltronic Halbleitermat Verfahren zur materialabtragenden Bearbeitung der Kanten von Halbleiterscheiben
US6833291B2 (en) * 2001-08-16 2004-12-21 Micron Technology, Inc. Semiconductor processing methods
JP4162892B2 (ja) 2002-01-11 2008-10-08 日鉱金属株式会社 半導体ウェハおよびその製造方法
WO2003077297A1 (fr) * 2002-03-14 2003-09-18 Disco Corporation Procede de meulage de la surface arriere d'une plaquette semi-conductrice
US7258931B2 (en) * 2002-08-29 2007-08-21 Samsung Electronics Co., Ltd. Semiconductor wafers having asymmetric edge profiles that facilitate high yield processing by inhibiting particulate contamination
JP3580311B1 (ja) * 2003-03-28 2004-10-20 住友電気工業株式会社 表裏識別した矩形窒化物半導体基板
JP2005129676A (ja) * 2003-10-23 2005-05-19 Sumitomo Mitsubishi Silicon Corp Ｓｏｉ基板用シリコン基板、ｓｏｉ基板、及びそのｓｏｉ基板の製造方法
US7998865B2 (en) * 2005-05-31 2011-08-16 Texas Instruments Incorporated Systems and methods for removing wafer edge residue and debris using a residue remover mechanism
US20060266383A1 (en) * 2005-05-31 2006-11-30 Texas Instruments Incorporated Systems and methods for removing wafer edge residue and debris using a wafer clean solution
JP4939038B2 (ja) * 2005-11-09 2012-05-23 日立電線株式会社 Ｉｉｉ族窒化物半導体基板
JP4806261B2 (ja) * 2006-01-05 2011-11-02 パナソニック株式会社 窒化物系化合物半導体素子用ウェハーの製造方法
US7838387B2 (en) * 2006-01-13 2010-11-23 Sumco Corporation Method for manufacturing SOI wafer
TWI314758B (en) * 2006-04-20 2009-09-11 Touch Micro System Tech Wafer having an asymmetric edge profile and method of making the same
DE102006037267B4 (de) * 2006-08-09 2010-12-09 Siltronic Ag Verfahren zur Herstellung von Halbleiterscheiben mit hochpräzisem Kantenprofil
US8389099B1 (en) 2007-06-01 2013-03-05 Rubicon Technology, Inc. Asymmetrical wafer configurations and method for creating the same
TWI404164B (zh) * 2008-09-05 2013-08-01 Au Optronics Corp 基板辨識治具與基板的辨識方法
CN101354228B (zh) * 2008-09-24 2010-06-09 友达光电股份有限公司 基板辨识治具与基板的辨识方法
JP2020145272A (ja) * 2019-03-05 2020-09-10 トヨタ自動車株式会社 半導体ウエハ
CN113809149B (zh) * 2021-07-23 2023-12-12 上海先进半导体制造有限公司 晶圆、半导体元件及半导体元件处理方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1145392A (en) * 1967-03-08 1969-03-12 Ass Elect Ind Improvements in semi-conductor rectifiers
JPS6058579B2 (ja) * 1977-07-25 1985-12-20 日本電気株式会社 半導体ウエ−ハの製造方法
JPS55113332A (en) * 1979-02-23 1980-09-01 Hitachi Ltd Manufacture of wafer
JPH0624199B2 (ja) * 1982-07-30 1994-03-30 株式会社日立製作所 ウエハの加工方法
JPS6088535U (ja) * 1983-11-24 1985-06-18 住友電気工業株式会社 半導体ウエハ
JPS60224268A (ja) * 1984-04-20 1985-11-08 Meidensha Electric Mfg Co Ltd 電力用半導体素子

Also Published As

Publication number Publication date
DE69029596D1 (de) 1997-02-20
JPH02275613A (ja) 1990-11-09
EP0393951B1 (de) 1997-01-08
US5110764A (en) 1992-05-05
US5021862A (en) 1991-06-04
EP0393951A3 (de) 1991-07-03
EP0393951A2 (de) 1990-10-24
JPH0624179B2 (ja) 1994-03-30

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee