US5021862A - Beveled semiconductor silicon wafer and manufacturing method thereof - Google Patents

Beveled semiconductor silicon wafer and manufacturing method thereof Download PDF

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Publication number
US5021862A
US5021862A US07/505,475 US50547590A US5021862A US 5021862 A US5021862 A US 5021862A US 50547590 A US50547590 A US 50547590A US 5021862 A US5021862 A US 5021862A
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beveled
wafer
silicon wafer
semiconductor silicon
angle
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US07/505,475
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Nobuyoshi Ogino
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Shin Etsu Handotai Co Ltd
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Shin Etsu Handotai Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/161—Tapered edges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/21—Circular sheet or circular blank
    • Y10T428/219—Edge structure

Definitions

  • the present invention relates to a semiconductor silicon wafer used to manufacture a semiconductor integrated circuit (IC) (i.e. semiconductor silicon wafer for IC).
  • IC semiconductor integrated circuit
  • FIG. 3 shows a semiconductor silicon wafer for IC having symmetrical beveled portions 21a and 21b formed on the front and back surfaces thereof.
  • the beveled width w 1 of the beveled portion 21a of the front surface and the beveled angle ⁇ 1 of the front surface are set to such values that do not cause a crown along the wafer edge when photoresist is applied or an epitaxial layer is formed later on the front surface.
  • the beveled width w 1 of the front beveled portion 21a is set to a width equal to or larger than a prescribed value and the front beveled angle ⁇ 1 is set so that a crown is not formed in the application of photoresist or the subsequent formation of an epitaxial layer.
  • ⁇ 1 has a small value, e.g., 20° or less
  • the width of the remained outer circumference of the wafer is narrowed, in other words, the outer circumferential edge of the wafer has a sharp wedge-shaped cross section.
  • a semiconductor silicon wafer adapted for integrated circuits which has the beveled portions unsymmetrically formed with each other along the remained circumferential edges of the front and back surfaces thereof.
  • An angle between the inclining surface of the beveled portion and the main surface on the back surface side is selected larger than that between the inclining surface of the beveled portion and the main surface on the front surface.
  • the beveled depth of the back surface in the semiconductor silicon wafer mentioned above is selected larger than that of the front surface and the above respective angles are set such that the beveled portions formed on the front and back surfaces have the same beveled width.
  • a manufacturing method of a semiconductor silicon wafer in which the beveled portions of the front and back surfaces thereof are simultaneously formed by a grindstone having a grinding surface configuration which will conform with the inventive circumferential profile of the semiconductor silicon wafer after it is finished.
  • the front beveled portion and the back beveled portion are independently arranged so that the former can sufficiently prevent the occurrence a crown and the latter can prevent the semiconductor silicon wafer from being chipped.
  • the beveled portions formed on the front and back surface sides have the same beveled width, and thus when the front and back beveled portions are simultaneously ground by the grindstone having the grinding surface which will conform with the circumferential edges of the semiconductor silicon wafer after it is finished, the peripheral corners of the front and back surfaces are simultaneously applied against the grinding surface of the grindstone, and the semiconductor silicon wafer is ground and finished at both the peripheral edges.
  • applied force on one of the surfaces being ground is always supported by that on the other surface being ground, whereby the occurrence of undesirable strain due to grinding and chipping of the semiconductor silicon wafer can be prevented.
  • FIG. 1 is a diagram showing the circumferential edges and the vicinity thereof of an embodiment of a semiconductor silicon wafer according to the present invention
  • FIG. 2 is a diagram showing a semiconductor silicon wafer and the vicinity of the grinding surface of a grindstone used to grind the semiconductor silicon wafer;
  • FIG. 3 is a diagram showing the circumferential portion and the vicinity thereof of an embodiment of a conventional semiconductor silicon wafer.
  • FIG. 1 shows a semiconductor silicon wafer of the invention.
  • numeral 1 designates the semiconductor silicon wafer, and beveled portions 1a and 1b are formed around the circumferential edges of the silicon wafer 1, so that the sectional figure of the wafer 1 on a vertical plane including the center of the wafer 1 gives generally a trapezoid at the beveled periphery which consists of both beveled surfaces and the vertical edge therebetween.
  • the semiconductor silicon wafer 1 can be, for example, a semiconductor silicon wafer for IC having the beveled portions 1a and 1b formed unsymmetrically and used for forming a semiconductor integrated circuit.
  • R 1 and R 2 are rounded, the radii of curvature being shown as R 1 and R 2 , respectively.
  • R 1 and R 2 may be shaped simultaneously when the beveled portions are machined, or may be formed by etching after the beveled portions have been machined.
  • the back beveled depth d 4 is set to be the value which can prevent the semiconductor silicon wafer from being chipped or to be a value larger than that of the front one.
  • the values of w 3 , d 3 , w 4 and d 4 are, for example, set such that when the thickness T of the semiconductor silicon wafer 1 is 0.6 mm, w 3 is 300 ⁇ m, d 3 is 60 ⁇ m, w 4 is 300 ⁇ m, d 4 is 310 ⁇ m, R 1 is 200 ⁇ m, and R 2 is 400 ⁇ m.
  • an ingot of a silicon monocrystal is cut into round slices to provide a semiconductor silicon wafer 11 having a prescribed depth (numeral 11 is used to discriminate this wafer before the beveling from the semiconductor silicon wafer 1 in which the beveled portions 1a and 1b have already been formed).
  • the beveled portions 1a and 1b are formed using a grindstone 2 shown in FIG. 2.
  • the configuration of the grinding surfaces 2a, 2b, and 2c of the rotary grindstone 2 is in conformity with the predetermined configuration of the circumferential edges of the semiconductor silicon wafer 1 according to the invention. More specifically, the configurations of the grinding surfaces 2a, 2b, and 2c of the grindstone 2 are such that the circumferential edges of the semiconductor silicon wafer 1 according to the invention conform therewith.
  • the wafer 11 When the above semiconductor silicon wafer 11 is ground using this grindstone 2, the wafer 11 is gradually moved in the direction approaching the rotation axis of the grindstone 2, while it is rotated in the direction opposite to that of the grindstone 2, whereby the beveled portions 1a and 1b are formed along the circumferential edges of the semiconductor silicon wafer 11.
  • the front beveled portion 1a and 1b and the back beveled portion 1b can be differently shaped so that the former can sufficiently prevent the occurrence of a crown and the latter can prevent the semiconductor silicon wafer 1 from being chipped. More specifically, with respect to the above semiconductor silicon wafer 1, the effect of the back beveled portion thereof is more increased than that of a conventional wafer in preventing the wafer from being chipped in the following processing.
  • the beveled portions 1a and 1b formed on the front and back surface sides have the same widths w 3 and w 4 , and thus when the beveled portions 1a and 1b of the front and back surface sides are simultaneously formed using the grindstone having the grinding surfaces 2a, 2b, and 2c which will conform with the desired circumferential edges of the semiconductor silicon wafer 1 after it is finished, the corners of the front and back surfaces are simultaneously applied against the grinding surfaces 2a and 2c, whereby the grinding operation thereof is simultaneously started and finished.
  • the peripheral corners of the front and back surfaces can be simultaneously applied against the grinding surfaces 2a and 2c of the grindstone 2, and further the grinding operation of the semiconductor silicon wafer 1 is simultaneously started and finished.
  • the occurrence of undesirable strain due to grinding and thus the chipping of the semiconductor silicon wafer can be prevented.
  • beveled portions 1a and 1b are flatly depicted in the above example, one or both thereof may be formed to have curved surfaces.
  • the beveled portions 1a and 1b formed on both main surface sides of the semiconductor silicon wafer 1 are formed as curves.
  • the front beveled portion and the back beveled portion are differently shaped so that the former can sufficiently prevent the occurrence of a crown and the latter can prevent the semiconductor silicon wafer 1 from being chipped.
  • the beveled portions formed on both the main surface sides have the same beveled width in the first invention, and thus when the front and back beveled portions are simultaneously ground by the grindstone having the grinding surface which conforms with the predetermined circumferential edges of the semiconductor silicon wafer after it is finished, the peripheral corners of the front and back surfaces are simultaneously applied against the grinding surface of the grindstone, and further the grinding operation of the semiconductor silicon wafer is simultaneously started and then finished. As a result, the occurrence of undesirable strain due to grinding and the chipping of the semiconductor silicon wafer can be prevented.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

A semiconductor silicon wafer usable for integrated circuits has beveled portions unsymmetrically formed along circumferential edges of front and back surfaces thereof. An angle between an inclining surface of the beveled portion and a main surface on the back surface side is larger than that between the inclining surface of the beveled portion and the main surface on the front surface side. Therefore the circumferential edges are prevented from being chipped.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor silicon wafer used to manufacture a semiconductor integrated circuit (IC) (i.e. semiconductor silicon wafer for IC).
2. Description of the Related Art
FIG. 3 shows a semiconductor silicon wafer for IC having symmetrical beveled portions 21a and 21b formed on the front and back surfaces thereof.
The beveled portions 21a and 21b of the semiconductor silicon wafer 21 are arranged as follows. Assuming that the beveled portion 21a on the front surface has a beveled width w1 and a beveled depth d1, and the beveled portion 21b on the back surface thereof has a beveled width w2 and a beveled depth d2, w1 =w2, and d1 =d2, and the angle θ1 between the inclining surface of the beveled portion 21a and the main surface on the front surface side [θ1 =arc tan(d1 /w1)] is equal to the angle θ2 between the inclining surface of the beveled portion 21b and the main surface on the back surface side [θ2 =arc tan(d2 /w2)]. Note that, in this case, the beveled width w1 of the beveled portion 21a of the front surface and the beveled angle θ1 of the front surface are set to such values that do not cause a crown along the wafer edge when photoresist is applied or an epitaxial layer is formed later on the front surface.
Nevertheless, the following problems arise in the above technology.
As described above, according to the above semiconductor silicon wafer 21, the beveled width w1 of the front beveled portion 21a is set to a width equal to or larger than a prescribed value and the front beveled angle θ1 is set so that a crown is not formed in the application of photoresist or the subsequent formation of an epitaxial layer. Along with the above consideration, the equations w1 =w2 and d1 =d2 are observed and the beveling therefore is symmetrically effected on the front and back surfaces, and thus the beveling of the back surface gives an adverse effect of chipping due to too much beveling, aside from the above-mentioned effect of the beveling of the front surface.
More specifically, when θ1 has a small value, e.g., 20° or less, the width of the remained outer circumference of the wafer is narrowed, in other words, the outer circumferential edge of the wafer has a sharp wedge-shaped cross section. As a result, a problem arises in that the semiconductor silicon wafer is liable to be chipped off in the following processing.
SUMMARY OF THE INVENTION
Taking the above into consideration, it is an object of the present invention to provide a semiconductor silicon wafer and manufacturing method thereof capable of effectively preventing the silicon wafer from being chipped off.
Other objects and novel advantages of the present invention will be apparent from the following description and accompanying drawings.
To achieve the above object, according to one aspect of the present invention, there is provided a semiconductor silicon wafer adapted for integrated circuits, which has the beveled portions unsymmetrically formed with each other along the remained circumferential edges of the front and back surfaces thereof. An angle between the inclining surface of the beveled portion and the main surface on the back surface side is selected larger than that between the inclining surface of the beveled portion and the main surface on the front surface.
Further, according to another aspect of the present invention, the beveled depth of the back surface in the semiconductor silicon wafer mentioned above is selected larger than that of the front surface and the above respective angles are set such that the beveled portions formed on the front and back surfaces have the same beveled width.
Further, according to further aspect of the present invention, there is provided a manufacturing method of a semiconductor silicon wafer, in which the beveled portions of the front and back surfaces thereof are simultaneously formed by a grindstone having a grinding surface configuration which will conform with the inventive circumferential profile of the semiconductor silicon wafer after it is finished.
According to the present invention, since the angle between the inclining surface of the beveled portion and the main surface on the back surface side is selected larger than that on the front surface side to make the front and back beveled portions unsymmetrical, the front beveled portion and the back beveled portion are independently arranged so that the former can sufficiently prevent the occurrence a crown and the latter can prevent the semiconductor silicon wafer from being chipped.
Further, according to the present invention, the beveled portions formed on the front and back surface sides have the same beveled width, and thus when the front and back beveled portions are simultaneously ground by the grindstone having the grinding surface which will conform with the circumferential edges of the semiconductor silicon wafer after it is finished, the peripheral corners of the front and back surfaces are simultaneously applied against the grinding surface of the grindstone, and the semiconductor silicon wafer is ground and finished at both the peripheral edges. As a result, applied force on one of the surfaces being ground is always supported by that on the other surface being ground, whereby the occurrence of undesirable strain due to grinding and chipping of the semiconductor silicon wafer can be prevented.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram showing the circumferential edges and the vicinity thereof of an embodiment of a semiconductor silicon wafer according to the present invention;
FIG. 2 is a diagram showing a semiconductor silicon wafer and the vicinity of the grinding surface of a grindstone used to grind the semiconductor silicon wafer; and
FIG. 3 is a diagram showing the circumferential portion and the vicinity thereof of an embodiment of a conventional semiconductor silicon wafer.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
An embodiment of a semiconductor silicon wafer according to the present invention will be described below with reference to the drawings.
FIG. 1 shows a semiconductor silicon wafer of the invention.
In the figure, numeral 1 designates the semiconductor silicon wafer, and beveled portions 1a and 1b are formed around the circumferential edges of the silicon wafer 1, so that the sectional figure of the wafer 1 on a vertical plane including the center of the wafer 1 gives generally a trapezoid at the beveled periphery which consists of both beveled surfaces and the vertical edge therebetween. The semiconductor silicon wafer 1 can be, for example, a semiconductor silicon wafer for IC having the beveled portions 1a and 1b formed unsymmetrically and used for forming a semiconductor integrated circuit.
More specifically, the semiconductor silicon wafer 1 of the embodiment is such that the beveled width w3 of the beveled portion 1a on the front surface side is selected equal to the beveled width w4 of the beveled portion 1b on the back surface side, and the beveled angle θ4 of the back surface [θ4 =arc tan(d4 /w4)] is larger than the beveled angle θ3 of the front surface [θ3 =arc tan(d3 /w3)]. That is, the beveled depth d4 of the back surface is larger than the beveled depth d3 of the front surface.
Further, the outermost circumferential edges of the wafer at the beveled portions 1a and 1b are rounded, the radii of curvature being shown as R1 and R2, respectively. These R1 and R2 may be shaped simultaneously when the beveled portions are machined, or may be formed by etching after the beveled portions have been machined.
The front beveled width w3 and the beveled angle θ3 [=arc tan(d3 /w3)] are set to be such values that do not cause a crown in the application of photoresist and the following formation of an epitaxial layer. In addition, the back beveled depth d4 is set to be the value which can prevent the semiconductor silicon wafer from being chipped or to be a value larger than that of the front one. The values of w3, d3, w4 and d4 are, for example, set such that when the thickness T of the semiconductor silicon wafer 1 is 0.6 mm, w3 is 300 μm, d3 is 60 μm, w4 is 300 μm, d4 is 310 μm, R1 is 200 μm, and R2 is 400 μm.
Next, a method of manufacturing the above semiconductor silicon wafer 1 will be described.
First, an ingot of a silicon monocrystal is cut into round slices to provide a semiconductor silicon wafer 11 having a prescribed depth (numeral 11 is used to discriminate this wafer before the beveling from the semiconductor silicon wafer 1 in which the beveled portions 1a and 1b have already been formed). Next, the beveled portions 1a and 1b are formed using a grindstone 2 shown in FIG. 2.
To describe here the grinding surfaces 2a, 2b, and 2c of the rotary grindstone 2 about an axis parallel with the perpendicular to the main surface of a wafer to be beveled shown in FIG. 2, the configuration of the grinding surfaces 2a, 2b, and 2c of the grindstone 2 is in conformity with the predetermined configuration of the circumferential edges of the semiconductor silicon wafer 1 according to the invention. More specifically, the configurations of the grinding surfaces 2a, 2b, and 2c of the grindstone 2 are such that the circumferential edges of the semiconductor silicon wafer 1 according to the invention conform therewith.
When the above semiconductor silicon wafer 11 is ground using this grindstone 2, the wafer 11 is gradually moved in the direction approaching the rotation axis of the grindstone 2, while it is rotated in the direction opposite to that of the grindstone 2, whereby the beveled portions 1a and 1b are formed along the circumferential edges of the semiconductor silicon wafer 11.
The following effects can be obtained by the semiconductor silicon wafer 1 of the above embodiment and the manufacturing method thereof.
For the above semiconductor silicon wafer 1, since the angle θ4 between the inclining surface of the back beveled portion 1b and the main surface on the back surface side (the beveling angle of the back surface) is larger than the angle θ3 between the inclining surface of the beveled portion 1a and the main surface on the front surface side (the beveling angle of the front surface), and the beveled portions 1a and 1b of the front and back surfaces are made unsymmetrical, the front beveled portion 1a and 1b and the back beveled portion 1b can be differently shaped so that the former can sufficiently prevent the occurrence of a crown and the latter can prevent the semiconductor silicon wafer 1 from being chipped. More specifically, with respect to the above semiconductor silicon wafer 1, the effect of the back beveled portion thereof is more increased than that of a conventional wafer in preventing the wafer from being chipped in the following processing.
Further, the beveled portions 1a and 1b formed on the front and back surface sides have the same widths w3 and w4, and thus when the beveled portions 1a and 1b of the front and back surface sides are simultaneously formed using the grindstone having the grinding surfaces 2a, 2b, and 2c which will conform with the desired circumferential edges of the semiconductor silicon wafer 1 after it is finished, the corners of the front and back surfaces are simultaneously applied against the grinding surfaces 2a and 2c, whereby the grinding operation thereof is simultaneously started and finished. As a result, while the beveled portions 1a and 1b are ground, pressure on one of the surfaces being ground is always supported by that on the other surface being ground, whereby the occurrence of undesirable strain due to grinding and thus the chipping of the semiconductor silicon wafer can be prevented.
Further, according to the above manufacturing method, since the beveled portions 1a and 1b of the front and back surfaces are simultaneously formed by the grinder 2 having the grinding surfaces 2a, 2b, and 2c which will conform with the inventive circumferential edges of the semiconductor silicon wafer 1 after it is finished, the peripheral corners of the front and back surfaces can be simultaneously applied against the grinding surfaces 2a and 2c of the grindstone 2, and further the grinding operation of the semiconductor silicon wafer 1 is simultaneously started and finished. As a result, the occurrence of undesirable strain due to grinding and thus the chipping of the semiconductor silicon wafer can be prevented.
Although the present invention effected by the inventor has been described above in detail with reference to one embodiment, the invention is not limited to the above embodiment, but it is obvious that various modifications can be made within the scope of the invention and which do not depart from the spirit of the invention.
For example, although the beveled portions 1a and 1b are flatly depicted in the above example, one or both thereof may be formed to have curved surfaces. In this case, the beveled portions 1a and 1b formed on both main surface sides of the semiconductor silicon wafer 1 are formed as curves.
The effects provided by the typical inventions disclosed in this application will be simply described below.
According to the present invention, since the angle between the inclining surface of the beveled portion and the main surface on the back surface side is larger than that on the front surface side to make the front and back beveled portions unsymmetrical, the front beveled portion and the back beveled portion are differently shaped so that the former can sufficiently prevent the occurrence of a crown and the latter can prevent the semiconductor silicon wafer 1 from being chipped. Further, according to the present invention, the beveled portions formed on both the main surface sides have the same beveled width in the first invention, and thus when the front and back beveled portions are simultaneously ground by the grindstone having the grinding surface which conforms with the predetermined circumferential edges of the semiconductor silicon wafer after it is finished, the peripheral corners of the front and back surfaces are simultaneously applied against the grinding surface of the grindstone, and further the grinding operation of the semiconductor silicon wafer is simultaneously started and then finished. As a result, the occurrence of undesirable strain due to grinding and the chipping of the semiconductor silicon wafer can be prevented.

Claims (4)

What is claimed is:
1. A semiconductor silicon wafer usable for integrated circuits, said wafer comprising first and second beveled portions unsymmetrically formed along circumferential edges of front and back sides respectively of said wafer, wherein a first angle located between a plane containing an inclining surface of the second beveled portion and a plane containing a main surface on the back side of said wafer, said first angle being located adjacent to the main surface on the back side of said wafer and being external to said wafer, is larger than a second angle located between the plane containing an inclining surface of the first beveled portion and a plane of a main surface on the front side of said wafer, said second angle being adjacent to the main surface on the front side of said wafer and being external to said wafer, whereby the circumferential edges of said wafer are prevented from being chipped.
2. A semiconductor silicon wafer usable for integrated circuits, said wafer comprising beveled portions unsymmetrically formed along circumferential edges of front and back sides of said wafer, a first angle between an inclining surface of the beveled portion and a main surface on the back side of said wafer being larger than a second angle between an inclining surface of the beveled portion and a main surface on the front side of said wafer, a beveled depth of the beveled portion on the back side being larger than a beveled depth of the beveled portion on the front side, and said respective angles being selected such that the beveled portions formed on the front and back sides have the same beveled radial width, whereby said circumferential edges are prevented from being chipped.
3. The semiconductor silicon wafer of claim 1, wherein said wafer further comprises a flat edge surface located between the beveled portions.
4. The semiconductor silicon wafer of claim 2, wherein said wafer comprises a flat edge surface located between the beveled portions.
US07/505,475 1989-04-17 1990-04-06 Beveled semiconductor silicon wafer and manufacturing method thereof Expired - Lifetime US5021862A (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5751055A (en) * 1994-02-12 1998-05-12 Shin-Etsu Handotai Co., Ltd. Semiconductor single crystalline substrate and method for production thereof
US6454514B2 (en) * 1998-07-08 2002-09-24 Semitool, Inc. Microelectronic workpiece support and apparatus using the support
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US20040097084A1 (en) * 2002-03-14 2004-05-20 Kazuya Fukuda Method for grinding rear surface of semiconductor wafer
US20070105258A1 (en) * 2005-11-09 2007-05-10 Takehiro Yoshida Group III nitride semiconductor substrate
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US6454514B2 (en) * 1998-07-08 2002-09-24 Semitool, Inc. Microelectronic workpiece support and apparatus using the support
US20040097084A1 (en) * 2002-03-14 2004-05-20 Kazuya Fukuda Method for grinding rear surface of semiconductor wafer
US20040041143A1 (en) * 2002-08-29 2004-03-04 Kim Gi-Jung Semiconductor wafers having asymmetric edge profiles that facilitate high yield processing by inhibiting particulate contamination and methods of forming same
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US8389099B1 (en) 2007-06-01 2013-03-05 Rubicon Technology, Inc. Asymmetrical wafer configurations and method for creating the same
US9390906B1 (en) 2007-06-01 2016-07-12 Rubicon Technology, Inc. Method for creating asymmetrical wafer
CN113809149A (en) * 2021-07-23 2021-12-17 上海先进半导体制造有限公司 Wafer, semiconductor device and semiconductor device processing method
CN113809149B (en) * 2021-07-23 2023-12-12 上海先进半导体制造有限公司 Wafer, semiconductor device and semiconductor device processing method

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JPH0624179B2 (en) 1994-03-30
DE69029596D1 (en) 1997-02-20
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EP0393951A2 (en) 1990-10-24
DE69029596T2 (en) 1997-07-10

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