US20090023364A1 - Method of making a wafer having an asymmetric edge profile - Google Patents

Method of making a wafer having an asymmetric edge profile Download PDF

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Publication number
US20090023364A1
US20090023364A1 US12/212,653 US21265308A US2009023364A1 US 20090023364 A1 US20090023364 A1 US 20090023364A1 US 21265308 A US21265308 A US 21265308A US 2009023364 A1 US2009023364 A1 US 2009023364A1
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Prior art keywords
wafer
main surface
edge profile
edge region
edge
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US12/212,653
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Chih-Ping Kuo
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Touch Micro System Technology Inc
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Individual
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Priority to US12/212,653 priority Critical patent/US20090023364A1/en
Assigned to TOUCH MICRO-SYSTEM TECHNOLOGY INC. reassignment TOUCH MICRO-SYSTEM TECHNOLOGY INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KUO, CHIH-PING
Publication of US20090023364A1 publication Critical patent/US20090023364A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/21—Circular sheet or circular blank
    • Y10T428/219—Edge structure

Definitions

  • the invention relates to a wafer having an asymmetric edge profile and a method of making the same, and more particularly, to a low stress wafer and a method of making the same.
  • Wafers are important bases of fabricating ultra-large scale integrated (ULSI) circuit components. With the development of crystal growth technologies, the diameters of wafers have increased from 25 millimeters in the early days of the technology to 300 millimeters (12 inches) at present.
  • the fabricating process of the wafers includes the following main steps. First, a semiconductor liquid raw material, such as silicon, is prepared. Subsequently, a crystal pulling process is performed utilizing a seed to form a columnar ingot. Next, the ingot is cut into a plurality of disk-like wafers by slicing.
  • the wafers are stored in cassettes, and clipped by robots so as to transfer the wafers to each process unit.
  • the edge region of a wafer is perpendicular to the first main surface (front side) and the second surface (back side) of the wafer, the wafer may easily stick in the cassettes or be damaged by the robots' clipping.
  • the perpendicular edge region of the wafer may easily crack due to the stress generated by temperature change in the following processes.
  • the edge region of a wafer should be polished after the wafer is formed, so that the wafer includes an arc-shaped edge profile.
  • FIG. 1 is a schematic diagram of a prior art standard wafer.
  • the standard wafer 10 includes a first main surface 12 , a second main surface 14 , and an edge region 16 .
  • the edge region 16 turns into an arc-shaped edge profile, where the edge profile is symmetric with respect to a central line of the first main surface 12 and the second main surface 14 . This feature prevents the standard wafer 10 from sticking in the cassettes or being damaged by the robots' clipping, and the standard wafer 10 is thus protected.
  • the thickness of the standard wafer 10 is changed according to the size of its diameter.
  • the thickness of the standard wafer 10 having a diameter of 8 inches is usually about 725 micrometers.
  • the standard wafer 10 can prevent the aforementioned problems of cracking and damage.
  • some processes such as the micro-electromechanical system (MEMS) processes, use thinned wafers and the thicknesses of said wafers must be in the range of 50 to 250 micrometers. In consideration of these processes, the probability of damaging and cracking occurring to the standard wafer 10 is greatly increased.
  • FIG. 2 is a schematic diagram of a thinned standard wafer. As shown in FIG.
  • the thickness of the standard wafer 10 is reduced from 725 micrometers to a thickness less than 250 micrometers (for instance, to a thickness of 200 micrometers) so as to fit the processing requirement, or other factors.
  • an acute angle is formed in the edge region 16 of the standard wafer 10 , the edge region 16 being in the shape of a knife.
  • the standard wafer 10 has an increased likelihood of sticking in the cassettes.
  • the acute edge profile causes the stress of the standard wafer 10 to increase, so the probability of cracking to the standard wafer 10 is also greatly increased.
  • a wafer having an asymmetric edge profile includes a disk-like body, and the disk-like body includes a first main surface, a second main surface parallel to the first main surface, and an edge region.
  • the first main surface and the second main surface define a central line between them, and the edge region has an edge profile, the edge profile being asymmetric with respect to the central line of the first main surface and the second main surface.
  • FIG. 1 is a schematic diagram of a prior art standard wafer.
  • FIG. 2 is a schematic diagram of a thinned standard wafer.
  • FIGS. 3 to 5 are schematic diagrams of a method of fabricating a wafer having an asymmetric edge profile according to a preferred embodiment of the present invention.
  • FIG. 6 is a schematic diagram of the wafer, which is the same wafer in FIG. 5 , but is thinned.
  • FIGS. 3 to 5 are schematic diagrams of a method of fabricating a wafer having an asymmetric edge profile according to a preferred embodiment of the present invention.
  • a wafer 30 is first provided.
  • the present invention takes a wafer with a diameter of 8 inches and a thickness of 725 micrometers as an example for illustrating the characteristics of the present invention, but the application is not limited to this example.
  • the wafer 30 comprises a disk-like body 32 , a first main surface 34 , a second main surface 36 parallel to the first main surface 34 , and an edge region 38 perpendicular to the first main surface 34 and the second main surface 36 , wherein the first main surface 34 and the second main surface 36 define a central line C 1 between them. Subsequently, the wafer 30 is cut along an angle ⁇ from a point G 1 in the second main surface 36 of the wafer 30 , so as to form a first inclined surface S 1 in the edge region 38 . Specifically speaking, in this preferred embodiment, the minimum distance between the point G 1 and a terminal point of the second main surface 36 is 0.499 millimeters, and the angle ⁇ is 24 degrees.
  • the edge region 38 is polished by utilizing a point O 1 , which does not lie in the central line C 1 , to be a center of curvature, and utilizing a predetermined radius R of curvature, so as to form an arc-shaped surface S 2 .
  • the minimum distance between the point O 1 and the edge region 38 is 0.6 millimeters
  • the minimum distance between the point O 1 and the first main surface 34 is 0.205 millimeters
  • the radius of curvature is 0.6 millimeters.
  • the wafer 30 is thereafter cut along an angle ⁇ from a point G 2 in the edge region 38 of the wafer 30 , so as to form a second inclined surface S 3 in the edge region 38 .
  • the minimum distance between the point G 2 and the first main surface 34 is 0.07 millimeters, and the angle ⁇ is 43 degrees.
  • the wafer 30 of the present invention has an asymmetric edge profile that consists of the first inclined surface S 1 , the arc-shaped surface S 2 , and the second inclined surface S 3 .
  • an included angle between a tangential line to any point on the edge profile and the first main surface 34 or the second main surface 36 is always an obtuse angle, whether the wafer 30 is at its initial thickness or the wafer 30 is thinned for the following processes. This effectively decreases the stress, and the probability of cracking to the wafer 30 occurring.
  • the asymmetric edge profile consisting of the first inclined surface S 1 and the arc-shaped surface S 2 is merely a preferred embodiment of the present invention, and the edge profile of the wafer 30 is not limited to this embodiment.
  • the specification of the inclined surface or of the arc-shaped surface can be adjusted by an appropriate degree, the edge profile may merely consist of a single arc-shaped surface, or the edge profile can consist of a plurality of arc-shaped surfaces. Therefore, no matter what thickness the wafer 30 is during the processes, the wafer 30 has a comparatively low stress.
  • FIG. 6 is a schematic diagram of the wafer 30 , which is the same wafer as in FIG. 5 , but is thinned. As shown in FIG. 6 , when the thickness of the wafer 30 is reduced to a range of 50 to 250 micrometers, the included angle between a tangential line to any point on the edge profile and the first main surface 34 or the second main surface 36 is still an obtuse angle. For this reason, the present invention can reduce the probability of cracking, and increase the yield.
  • the wafer of the present invention has an asymmetric edge profile, the included angle between a tangential line to any point on the edge profile and the first main surface or the second main surface is always an obtuse angle, whether the wafer is at its initial thickness before any processes have been performed, or the wafer is thinned to another thickness during the processes.
  • the present invention can effectively reduce the stress, reduce the probability of cracking, and prevent the wafer from sticking in the cassettes.

Abstract

A wafer having an asymmetric edge profile is provided. The wafer has a disk-like body. The disc-like body has a first main surface, a second main surface parallel to the first main surface, and an edge region. The disk-like body has a central line defined between the first main surface and the second main surface, the edge region has an edge profile, and the edge profile is asymmetric with respect to the central line of the first main surface and the second main surface.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This divisional application claims the benefit of co-pending U.S. application Ser. No. 11/456,090, filed on Jul. 7, 2006 and included herein by reference.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The invention relates to a wafer having an asymmetric edge profile and a method of making the same, and more particularly, to a low stress wafer and a method of making the same.
  • 2. Description of the Prior Art
  • Wafers are important bases of fabricating ultra-large scale integrated (ULSI) circuit components. With the development of crystal growth technologies, the diameters of wafers have increased from 25 millimeters in the early days of the technology to 300 millimeters (12 inches) at present. The fabricating process of the wafers includes the following main steps. First, a semiconductor liquid raw material, such as silicon, is prepared. Subsequently, a crystal pulling process is performed utilizing a seed to form a columnar ingot. Next, the ingot is cut into a plurality of disk-like wafers by slicing.
  • The wafers are stored in cassettes, and clipped by robots so as to transfer the wafers to each process unit. As a result, if the edge region of a wafer is perpendicular to the first main surface (front side) and the second surface (back side) of the wafer, the wafer may easily stick in the cassettes or be damaged by the robots' clipping. Furthermore, the perpendicular edge region of the wafer may easily crack due to the stress generated by temperature change in the following processes. Thus, the edge region of a wafer should be polished after the wafer is formed, so that the wafer includes an arc-shaped edge profile.
  • Please refer to FIG. 1. FIG. 1 is a schematic diagram of a prior art standard wafer. As shown in FIG. 1, the standard wafer 10 includes a first main surface 12, a second main surface 14, and an edge region 16. After edge polishing, the edge region 16 turns into an arc-shaped edge profile, where the edge profile is symmetric with respect to a central line of the first main surface 12 and the second main surface 14. This feature prevents the standard wafer 10 from sticking in the cassettes or being damaged by the robots' clipping, and the standard wafer 10 is thus protected.
  • Generally speaking, the thickness of the standard wafer 10 is changed according to the size of its diameter. For example, the thickness of the standard wafer 10 having a diameter of 8 inches is usually about 725 micrometers. With regard to the general semiconductor processes, the standard wafer 10 can prevent the aforementioned problems of cracking and damage. However, some processes, such as the micro-electromechanical system (MEMS) processes, use thinned wafers and the thicknesses of said wafers must be in the range of 50 to 250 micrometers. In consideration of these processes, the probability of damaging and cracking occurring to the standard wafer 10 is greatly increased. Please refer to FIG. 2. FIG. 2 is a schematic diagram of a thinned standard wafer. As shown in FIG. 2, the thickness of the standard wafer 10 is reduced from 725 micrometers to a thickness less than 250 micrometers (for instance, to a thickness of 200 micrometers) so as to fit the processing requirement, or other factors. In such a manner, an acute angle is formed in the edge region 16 of the standard wafer 10, the edge region 16 being in the shape of a knife. As a result, the standard wafer 10 has an increased likelihood of sticking in the cassettes. Meanwhile, the acute edge profile causes the stress of the standard wafer 10 to increase, so the probability of cracking to the standard wafer 10 is also greatly increased.
    • SUMMARY OF THE INVENTION
  • It is therefore an objective of the present invention to provide a wafer having an asymmetric edge profile, and a method of making the same, to reduce the probability of cracking to the wafer, and to increase the yield.
  • According to the present invention, a wafer having an asymmetric edge profile is provided. The above-mentioned wafer includes a disk-like body, and the disk-like body includes a first main surface, a second main surface parallel to the first main surface, and an edge region. The first main surface and the second main surface define a central line between them, and the edge region has an edge profile, the edge profile being asymmetric with respect to the central line of the first main surface and the second main surface.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic diagram of a prior art standard wafer.
  • FIG. 2 is a schematic diagram of a thinned standard wafer.
  • FIGS. 3 to 5 are schematic diagrams of a method of fabricating a wafer having an asymmetric edge profile according to a preferred embodiment of the present invention.
  • FIG. 6 is a schematic diagram of the wafer, which is the same wafer in FIG. 5, but is thinned.
    •  DETAILED DESCRIPTION
  • Please refer to FIGS. 3 to 5. FIGS. 3 to 5 are schematic diagrams of a method of fabricating a wafer having an asymmetric edge profile according to a preferred embodiment of the present invention. As shown in FIG. 3, a wafer 30 is first provided. The present invention takes a wafer with a diameter of 8 inches and a thickness of 725 micrometers as an example for illustrating the characteristics of the present invention, but the application is not limited to this example. The wafer 30 comprises a disk-like body 32, a first main surface 34, a second main surface 36 parallel to the first main surface 34, and an edge region 38 perpendicular to the first main surface 34 and the second main surface 36, wherein the first main surface 34 and the second main surface 36 define a central line C1 between them. Subsequently, the wafer 30 is cut along an angle α from a point G1 in the second main surface 36 of the wafer 30, so as to form a first inclined surface S1 in the edge region 38. Specifically speaking, in this preferred embodiment, the minimum distance between the point G1 and a terminal point of the second main surface 36 is 0.499 millimeters, and the angle α is 24 degrees.
  • Next, as shown in FIG. 4, the edge region 38 is polished by utilizing a point O1, which does not lie in the central line C1, to be a center of curvature, and utilizing a predetermined radius R of curvature, so as to form an arc-shaped surface S2. In this preferred embodiment, the minimum distance between the point O1 and the edge region 38 is 0.6 millimeters, the minimum distance between the point O1 and the first main surface 34 is 0.205 millimeters, and the radius of curvature is 0.6 millimeters.
  • As shown in FIG. 5, the wafer 30 is thereafter cut along an angle β from a point G2 in the edge region 38 of the wafer 30, so as to form a second inclined surface S3 in the edge region 38. In this preferred embodiment, the minimum distance between the point G2 and the first main surface 34 is 0.07 millimeters, and the angle β is 43 degrees.
  • Hence, the wafer 30 of the present invention has an asymmetric edge profile that consists of the first inclined surface S1, the arc-shaped surface S2, and the second inclined surface S3. As a result, an included angle between a tangential line to any point on the edge profile and the first main surface 34 or the second main surface 36 is always an obtuse angle, whether the wafer 30 is at its initial thickness or the wafer 30 is thinned for the following processes. This effectively decreases the stress, and the probability of cracking to the wafer 30 occurring. It should be noted that the asymmetric edge profile consisting of the first inclined surface S1 and the arc-shaped surface S2 is merely a preferred embodiment of the present invention, and the edge profile of the wafer 30 is not limited to this embodiment. For instance, the specification of the inclined surface or of the arc-shaped surface can be adjusted by an appropriate degree, the edge profile may merely consist of a single arc-shaped surface, or the edge profile can consist of a plurality of arc-shaped surfaces. Therefore, no matter what thickness the wafer 30 is during the processes, the wafer 30 has a comparatively low stress.
  • Please refer to FIG. 6. FIG. 6 is a schematic diagram of the wafer 30, which is the same wafer as in FIG. 5, but is thinned. As shown in FIG. 6, when the thickness of the wafer 30 is reduced to a range of 50 to 250 micrometers, the included angle between a tangential line to any point on the edge profile and the first main surface 34 or the second main surface 36 is still an obtuse angle. For this reason, the present invention can reduce the probability of cracking, and increase the yield.
  • In sum, because the wafer of the present invention has an asymmetric edge profile, the included angle between a tangential line to any point on the edge profile and the first main surface or the second main surface is always an obtuse angle, whether the wafer is at its initial thickness before any processes have been performed, or the wafer is thinned to another thickness during the processes. Thus, the present invention can effectively reduce the stress, reduce the probability of cracking, and prevent the wafer from sticking in the cassettes.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (4)

1. A method of fabricating a wafer having an asymmetric edge profile comprising:
providing a wafer, the wafer comprising a first main surface, a second main surface parallel to the first main surface, and an edge region perpendicular to the first main surface and the second main surface, wherein the first main surface and the second main surface define a central line between them;
polishing the edge region of the wafer, so that the edge region has an edge profile asymmetric with respect to the central line of the first main surface and the second main surface;
thinning the wafer from the second main surface until the wafer reaches a predetermined thickness, an included angle between a tangential line to any point on the edge profile and the first main surface or the second main surface being an obtuse angle according to the predetermined thickness.
2. The method of claim 1, wherein the predetermined thickness is in a range of 50 to 250 micrometers.
3. The method of claim 1, wherein the step of polishing the edge region of the wafer comprises:
polishing the edge region by utilizing a predetermined radius of curvature; and
utilizing a point which does not lie in the central line to be a center of curvature, so as to form the edge profile.
4. The method of claim 3 further comprising:
polishing the edge region to make the edge profile comprise at least an inclined surface.
US12/212,653 2006-04-20 2008-09-18 Method of making a wafer having an asymmetric edge profile Abandoned US20090023364A1 (en)

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TW095114099A TWI314758B (en) 2006-04-20 2006-04-20 Wafer having an asymmetric edge profile and method of making the same
TW095114099 2006-04-20
US11/456,090 US20070248786A1 (en) 2006-04-20 2006-07-07 Wafer having an asymmetric edge profile and method of making the same
US12/212,653 US20090023364A1 (en) 2006-04-20 2008-09-18 Method of making a wafer having an asymmetric edge profile

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US20170309579A1 (en) * 2016-04-25 2017-10-26 Siliconware Precision Industries Co., Ltd. Electronic package and substrate structure
CN108538790A (en) * 2017-03-03 2018-09-14 矽品精密工业股份有限公司 Substrate structure, manufacturing method thereof and electronic package

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US8710665B2 (en) * 2008-10-06 2014-04-29 Infineon Technologies Ag Electronic component, a semiconductor wafer and a method for producing an electronic component
US20110129648A1 (en) * 2009-11-30 2011-06-02 Yabei Gu Glass sheet article with double-tapered asymmetric edge
JP2020145272A (en) * 2019-03-05 2020-09-10 トヨタ自動車株式会社 Semiconductor wafer

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US20170309579A1 (en) * 2016-04-25 2017-10-26 Siliconware Precision Industries Co., Ltd. Electronic package and substrate structure
US10763223B2 (en) * 2016-04-25 2020-09-01 Siliconware Precision Industries Co., Ltd. Substrate structure having chamfers
US11227842B2 (en) 2016-04-25 2022-01-18 Siliconware Precision Industries Co., Ltd. Electronic package and substrate structure having chamfers
CN108538790A (en) * 2017-03-03 2018-09-14 矽品精密工业股份有限公司 Substrate structure, manufacturing method thereof and electronic package
US11056442B2 (en) * 2017-03-03 2021-07-06 Siliconware Precision Industries Co., Ltd. Substrate structure, electronic package having the same, and method for fabricating the same
US11527491B2 (en) 2017-03-03 2022-12-13 Siliconware Precision Industries Co., Ltd Method for fabricating substrate structure

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US20070248786A1 (en) 2007-10-25
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