JP2004111799A - Manufacture of semiconductor chip - Google Patents

Manufacture of semiconductor chip Download PDF

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Publication number
JP2004111799A
JP2004111799A JP2002274923A JP2002274923A JP2004111799A JP 2004111799 A JP2004111799 A JP 2004111799A JP 2002274923 A JP2002274923 A JP 2002274923A JP 2002274923 A JP2002274923 A JP 2002274923A JP 2004111799 A JP2004111799 A JP 2004111799A
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JP
Japan
Prior art keywords
wafer
chamfered
chamfering
semiconductor chip
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002274923A
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Japanese (ja)
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JP2004111799A5 (en
Inventor
Hiroshi Takabayashi
高林 広
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
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Canon Inc
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Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2002274923A priority Critical patent/JP2004111799A/en
Publication of JP2004111799A publication Critical patent/JP2004111799A/en
Publication of JP2004111799A5 publication Critical patent/JP2004111799A5/ja
Pending legal-status Critical Current

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  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the occurrence of cracking or chipping in the periphery of a semiconductor wafer, which is a problem in reducing the thickness of the wafer in the manufacture of a semiconductor chip. <P>SOLUTION: The manufacture of a semiconductor chip comprises; a step (A) for sticking a protective tape to the surface of a chamfered wafer, on which a number of semiconductor chips are formed; a step (B) for thinning the rear of the wafer; a step (C) for sticking a dicing tape to the rear of the wafer, and for mounting the wafer on a dicing frame; and a step (D) for separating the protective film from the surface of the wafer. Prior to the step (A), the edge surfaces of the wafer are rechamfered, the protective tape is stuck to the surface of the rechamfered wafer, and the thickness of the wafer is reduced by grinding/polishing/etching the rear surface. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、半導体ウエハーを薄片化して半導体チップを製造する方法、特にウエハーの薄化に際して問題となるウエハー周辺部のクラックやチッピングを防止して半導体チップを製造する方法に関する。
【0002】
【従来の技術】
特開平5−29455号公報には、半導体ウエハーを薄化して半導体チップを製造する方法が記載されている。具体的には、当該公報に記載の半導体チップの製造方法は、図4に示す内容のものであって、図4(a)に示すように半導体ウエハー1の表面に表面保護シート2を貼った後、図4(b)に示すように前記半導体ウエハーの裏面を研削する工程と、図4(c)に示すように前記半導体ウエハーの裏面に裏面シート3を貼ると同時に前記裏面シート外周にフレーム4を貼る工程と、図4(d)に示すように前記表面保護シート2をはがして図4(e)に示すように前記記半導体ウエハーを個々のチップに分割するダイシング工程とからなるものである。
【0003】
【発明が解決しようとする課題】
上記公報に記載の方法において製造する半導体チップの厚さを25〜50μm(具体的には、例えば50μm程度)に形成しようとすると、半導体ウエハーを薄化する工程でチッピングやクラックが前記ウエハーの端面に発生して、内部の素子を破壊してしまったり、或いはその後の工程のダイシングテープの貼付け工程、マウント工程、ダイシング工程や薄化後のウエハーの搬送中に破損してしまい良品率が低下してしまうといった問題が生ずることがあることが判明した。こうした問題の生起は、半導体ウエハーの周辺端面部を、通常、ラウンド面取りと呼ばれる角を取った形状にして、前工程における冶具との接触時に傷や欠けが生じないようにすることに起因する。図1(a)及び図1(b)は、ラウンド面取された半導体ウエハーを薄化する際に生じる問題を説明するための図である。本発明者によるテストでは、特に所望の厚さが50μm以下の厚さになってくると薄化したウエハーの端面は物理的に鋭角になってしまい、ウエハー端面からのチッピングやクラックの発生頻度が多くなり上述した問題が生じ易くなることが判明した。
【0004】
【課題を解決するための手段】
本発明は、上記課題を解決した半導体チップの製造方法を提供する。本発明の半導体チップの製造方法は、半導体チップが多数形成されている面取りしたウエハーの表面に保護テープを貼り付ける工程(A)、前記ウエハーの裏面を薄化する工程(B)、前記ウエハーの裏面にダイシングテープを貼り、前記ウエハーをダイシング用フレームにマウントする工程(C)、及び前記ウエハー表面の保護テープを剥離する工程(D)を有する半導体チップの製造方法において、前記工程(A)の前に前記ウエハーの端面を再面取りし、前記再面取りしたウエハーの表面に前記保護テープを貼り付け、前記ウエハーの裏面を研削及び/又は研磨及び/又はエッチングして薄化することを特徴とする。
本発明の半導体チップの製造方法においては、前記ウエハー端面の再面取りは、略垂直の面取り角度で行い、且つ最初の面取りの始点と最初の面取りにおける所望厚さに到る点との間まで再面取りすることが好ましい。更に、前記再面取りが垂直部とR面取り部からなるものであることが好ましい。
【0005】
【実施態様例】
以下に、図を用いて本発明の実施態様例を説明するが、本発明はこれに限定されるものではない。
【0006】
本発明の第一の実施態様例を図1及び図3を用いて説明する。図1は、既に面取りされている半導体ウエハー(制御用ICウエハー)[図1(a)及び図1(b)]と本発明により前記ウエハーを再面取りして得られるウエハーの形態[図1(c)及び図1(d)]を示す。図3は、既に面取りされている半導体ウエハー(制御用ICウエハー)を再面取りした後、ウエハーの薄化、ウエハーの切断、及びチップ分離を順次行って半導体チップを製造する本発明の半導体チップの製造工程を示すフローチャートである。
【0007】
図1(a)は既に面取りされている半導体ウエハー(制御用ICウエハー)の外観図であり、図1(b)は図1(a)に示すウエハーの端面の拡大図であり、図1(c)は図1(a)に示すウエハーの端面を略垂直に再面取りした端面の拡大図であり、図1(d)は図1(c)に示す再面取りしたウエハーを薄化した後のウエハー端面の拡大図である。図1(a)乃至 図1(d)に徴して明らかなように、ウエハーの再面取りは、既存の面取り(最初に行った面取り)の始点と該既存の面取りの所望厚さに到る点との間まで再面取りすることで、前記再面取り時に薄化工程でウエハーの端面が物理的に鋭角になってしまうことがないので、ウエハー表面にダメージを与えることがなく、ウエハー端面からのチッピングやクラックの発生頻度が多くなることを防止することができる。 図1(c)に示すように再面取りした半導体ウエハー(図3の[制御用ICウエハー]−[端面の再研磨]参照)の表面に保護テープを貼り付け(図3の[表面保護テープ貼付け]参照)、該ウエハーの裏面を研削及び/又は研磨及び/又はエッチングすることで図1(d)に示すような薄化した(図3の[研削、研磨]参照)ウエハーを安定して作製することができる。
【0008】
その後、図3のフローチャートの[研削、研磨]以降の処理手順に従ってウエハーの裏面にダイシングテープを貼り、前記ウエハーをダイシング用フレームにマウントする工程と、前記ウエハー表面の保護テープを剥離する工程と、前記半導体ウエハーを個々のチップに分割するダイシング工程とを経てウエハーを半導体チップに個片化する。
【0009】
図2は本発明の第二の実施態様例を示す。 図2(c)及び図2(d)は、それぞれ図1(c)及び図1(d)に対応するものである。図2(c)は、既に面取りされている半導体ウエハー(制御用ICウエハー)の端面を略垂直に再面取りするとともに前記再面取りが垂直部とR面取り部からなる端面の拡大図であり、図2(d)は、図2(c)に示すウエハーを薄化した後の端面の拡大図である。
本実施態様例では、上記第一の実施態様例で示したように、ウエハーの再面取りの垂直部は既存の面取りの始点と既存の面取りの所望厚さに到る点との間まで再面取りし、更に前記再面取りしたウエハーの表面側を再面取りのR面取り部とすることで、再面取り時にウエハー表面側へのダメージをより一層防止することができる。薄化工程での効果は上記記第一の実施態様例と同様で、ウエハーの端面は物理的に鋭角になってしまうことがなく、ウエハー端面からのチッピングやクラックの発生頻度が多くなることを防止することができる。
【0010】
図2(c)に示すように再面取りしたウエハーの表面に、上記記第一の実施態様例で述べたように、保護テープを貼り付け、次いで前記ウエハーの裏面を研削及び/又は研磨及び/又はエッチングすることで図2(d)に示すような薄化したウエハーを安定して作製することができる。その後、上記記第一の実施態様例におけると同様に、図3のフローチャートの[研削、研磨]以降の処理手順に従って、ウエハーの裏面にダイシングテープを貼り、前記ウエハーをダイシング用フレームにマウントする工程と、前記ウエハー表面の保護テープを剥離する工程と、前記半導体ウエハーを個々のチップに分割するダイシング工程とを経てウエハーを半導体チップに個片化する。
【0011】
【発明の効果】
以上詳細に説明したように、本発明によれば、既に面取りされている半導体ウエハーの端面を再面取りし、その際既存の面取りの始点と既存の面取りの所望厚さに到る点との間まで再面取りし、その後前記ウエハーの表面に保護テープを貼り付け、前記ウエハーの裏面を研削及び/又は研磨及び/又はエッチングすることにことによりウエハー端面からのクラックを防止してウエハーの薄化を行うことができ、これによりその後の個片化工程における良品率の向上が達成される。 特にウエハーの厚さが50μm以下の超薄化と個片化とを可能とする上で極めて効果的である。更に、前記再面取りを垂直部とR面取り部からなるように構成することで、ウエハー表面側へのダメージをより一層減少せしめることができる。
【図面の簡単な説明】
【図1】本発明の第一の実施態様例を示す図である。
【図2】本発明の第二の実施態様例を示す図である。
【図3】本発明の半導体チップの製造方法の工程を示すフロー図である。
【図4】従来の半導体ウエハーを薄化して半導体チップを製造する方法の工程を示すフロー図である。
【符号の説明】
1 半導体ウエハー
2 表面保護シート
3 裏面シート
4 フレーム
11 半導体チップ(制御用IC)
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor chip by thinning a semiconductor wafer, and more particularly to a method of manufacturing a semiconductor chip by preventing cracks and chipping in a peripheral portion of a wafer which is a problem in thinning a wafer.
[0002]
[Prior art]
JP-A-5-29455 describes a method for manufacturing a semiconductor chip by thinning a semiconductor wafer. Specifically, the method of manufacturing a semiconductor chip described in this publication has the contents shown in FIG. 4, and a surface protection sheet 2 is attached to the surface of a semiconductor wafer 1 as shown in FIG. Thereafter, as shown in FIG. 4 (b), a step of grinding the back surface of the semiconductor wafer, and as shown in FIG. 4 (c), attaching a back sheet 3 to the back surface of the semiconductor wafer, and simultaneously forming a frame on the outer periphery of the back sheet. 4 and a dicing step of peeling off the surface protection sheet 2 as shown in FIG. 4 (d) and dividing the semiconductor wafer into individual chips as shown in FIG. 4 (e). is there.
[0003]
[Problems to be solved by the invention]
If an attempt is made to form a semiconductor chip having a thickness of 25 to 50 μm (specifically, for example, about 50 μm) by the method described in the above-mentioned publication, chipping or cracking may occur in the step of thinning the semiconductor wafer. And cause damage to the internal elements, or damage during the subsequent process of attaching the dicing tape, the mounting process, the dicing process, and the transfer of the wafer after thinning, resulting in a lower non-defective product rate. It has been found that there is a possibility that such a problem may occur. The occurrence of such a problem arises from the fact that the peripheral end face of the semiconductor wafer is usually formed into a rounded shape called a round chamfer so that no damage or chipping occurs at the time of contact with the jig in the previous process. FIGS. 1A and 1B are diagrams for explaining a problem that occurs when a round-chamfered semiconductor wafer is thinned. In the test by the present inventor, especially when the desired thickness becomes 50 μm or less, the edge face of the thinned wafer becomes physically acute, and the frequency of chipping and cracking from the wafer edge face decreases. It has been found that the above-mentioned problem tends to occur more frequently.
[0004]
[Means for Solving the Problems]
The present invention provides a method for manufacturing a semiconductor chip that solves the above-mentioned problems. In the method for manufacturing a semiconductor chip according to the present invention, a step (A) of attaching a protective tape to a chamfered wafer surface on which a large number of semiconductor chips are formed, a step (B) of thinning the back surface of the wafer, In the method for manufacturing a semiconductor chip, the method further comprises a step (C) of attaching a dicing tape to the back surface and mounting the wafer on a dicing frame, and a step (D) of peeling off the protective tape on the surface of the wafer. Before, the end surface of the wafer is re-chamfered, the protective tape is attached to the surface of the re-chamfered wafer, and the back surface of the wafer is thinned by grinding and / or polishing and / or etching. .
In the method of manufacturing a semiconductor chip according to the present invention, the re-chamfering of the wafer end face is performed at a substantially vertical chamfering angle, and the re-chamfering is performed between a starting point of the first chamfering and a point reaching a desired thickness in the first chamfering. It is preferable to chamfer. Further, it is preferable that the re-chamfering comprises a vertical portion and an R-chamfered portion.
[0005]
[Example of embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.
[0006]
A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a semiconductor wafer (control IC wafer) [FIG. 1 (a) and FIG. 1 (b)] which has been chamfered, and a wafer form obtained by re-chamfering the wafer according to the present invention [FIG. c) and FIG. 1 (d)]. FIG. 3 shows a semiconductor chip of the present invention in which a semiconductor chip (a control IC wafer) that has already been chamfered is re-chamfered, and then the thinning of the wafer, cutting of the wafer, and chip separation are sequentially performed to manufacture a semiconductor chip. It is a flowchart which shows a manufacturing process.
[0007]
FIG. 1A is an external view of a semiconductor wafer (control IC wafer) which has already been chamfered, and FIG. 1B is an enlarged view of an end face of the wafer shown in FIG. FIG. 1C is an enlarged view of the end face of the wafer shown in FIG. 1A, which is substantially vertically re-chamfered, and FIG. 1D is a view of the wafer after the thinned re-chamfered wafer shown in FIG. It is an enlarged view of a wafer end surface. As is apparent from FIGS. 1 (a) to 1 (d), the re-chamfering of the wafer is performed at the starting point of the existing chamfer (the first chamfering) and the point at which the desired thickness of the existing chamfer is reached. By re-chamfering, the edge of the wafer is not physically sharpened in the thinning process during the re-chamfering, so that the wafer surface is not damaged, and chipping from the wafer edge is performed. The frequency of occurrence of cracks and cracks can be prevented from increasing. As shown in FIG. 1 (c), a protective tape is attached to the surface of the re-chamfered semiconductor wafer (see [Control IC Wafer]-[Regrinding of the end face] in FIG. 3). ], And grinding and / or polishing and / or etching the back surface of the wafer to stably produce a thinned wafer as shown in FIG. 1D (see [grinding and polishing] in FIG. 3). can do.
[0008]
Thereafter, a dicing tape is attached to the back surface of the wafer according to the processing procedure after [grinding and polishing] in the flowchart of FIG. 3, and the step of mounting the wafer on a dicing frame; and the step of peeling off the protective tape on the surface of the wafer. Through the dicing step of dividing the semiconductor wafer into individual chips, the wafer is diced into semiconductor chips.
[0009]
FIG. 2 shows a second embodiment of the present invention. FIGS. 2C and 2D correspond to FIGS. 1C and 1D, respectively. FIG. 2 (c) is an enlarged view of an end face of a semiconductor wafer (control IC wafer) which has already been chamfered, which is substantially perpendicularly re-chamfered, and wherein the re-chamfering comprises a vertical portion and an R chamfered portion. FIG. 2D is an enlarged view of the end face after the wafer shown in FIG. 2C is thinned.
In this embodiment, as shown in the first embodiment above, the vertical portion of the re-chamfering of the wafer is re-chamfered between the starting point of the existing chamfer and the point where the existing chamfer reaches the desired thickness. Further, by making the front side of the re-chamfered wafer a R-chamfered portion for re-chamfering, damage to the wafer front side during the re-chamfering can be further prevented. The effect in the thinning step is the same as that of the first embodiment described above, and the end face of the wafer does not become a physical acute angle, and the frequency of chipping and cracking from the wafer end face increases. Can be prevented.
[0010]
As shown in the first embodiment, a protective tape is applied to the front surface of the wafer which has been re-chamfered as shown in FIG. 2 (c), and then the back surface of the wafer is ground and / or polished and / or ground. Alternatively, a thinned wafer as shown in FIG. 2D can be manufactured stably by etching. Then, as in the first embodiment described above, a dicing tape is attached to the back surface of the wafer and the wafer is mounted on a dicing frame according to the processing procedure after [grinding and polishing] in the flowchart of FIG. And a step of peeling off the protective tape on the wafer surface and a dicing step of dividing the semiconductor wafer into individual chips to singulate the wafer into semiconductor chips.
[0011]
【The invention's effect】
As described in detail above, according to the present invention, the end face of the semiconductor wafer that has already been chamfered is re-chamfered, and the distance between the starting point of the existing chamfer and the point reaching the desired thickness of the existing chamfer is obtained. Then, a protective tape is attached to the surface of the wafer, and the back surface of the wafer is ground and / or polished and / or etched to prevent cracks from the wafer end surface and to reduce the thickness of the wafer. Thus, an improvement in the non-defective rate in the subsequent individualization step is achieved. In particular, it is extremely effective in enabling ultra-thin wafers with a thickness of 50 μm or less and singulation. Further, by configuring the re-chamfering to include a vertical portion and an R-chamfered portion, damage to the wafer surface side can be further reduced.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first embodiment example of the present invention.
FIG. 2 is a diagram showing a second embodiment of the present invention.
FIG. 3 is a flowchart showing steps of a method for manufacturing a semiconductor chip of the present invention.
FIG. 4 is a flowchart showing steps of a conventional method for manufacturing a semiconductor chip by thinning a semiconductor wafer.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Surface protection sheet 3 Back sheet 4 Frame 11 Semiconductor chip (control IC)

Claims (3)

半導体チップが多数形成されている面取りしたウエハーの表面に保護テープを貼り付ける工程(A)、前記ウエハーの裏面を薄化する工程(B)、前記ウエハーの裏面にダイシングテープを貼り、前記ウエハーをダイシング用フレームにマウントする工程(C)、及び前記ウエハー表面の保護テープを剥離する工程(D)を有する半導体チップの製造方法において、前記工程(A)の前に前記ウエハーの端面を再面取りし、前記再面取りしたウエハーの表面に前記保護テープを貼り付け、前記ウエハーの裏面を研削及び/又は研磨及び/又はエッチングして薄化することを特徴とする半導体チップの製造方法。Attaching a protective tape to the surface of the chamfered wafer on which a large number of semiconductor chips are formed (A), thinning the back surface of the wafer (B), attaching a dicing tape to the back surface of the wafer, and attaching the wafer In a method for manufacturing a semiconductor chip having a step (C) of mounting on a dicing frame and a step (D) of peeling off a protective tape on the surface of the wafer, the end face of the wafer is chamfered before the step (A). A method of manufacturing a semiconductor chip, comprising: attaching the protective tape to the front surface of the re-chamfered wafer; and grinding and / or polishing and / or etching the back surface of the wafer to reduce the thickness. 前記ウエハー端面の再面取りは、略垂直の面取り角度で行い、且つ最初の面取りの始点と最初の面取りの所望厚さに到る点との間まで再面取りすることを特徴とする請求項1に記載の半導体チップの製造方法。The method of claim 1, wherein the re-chamfering of the wafer end surface is performed at a substantially vertical chamfering angle, and re-chamfering is performed between a starting point of the first chamfering and a point reaching a desired thickness of the first chamfering. A manufacturing method of the semiconductor chip described in the above. 前記再面取りが垂直部とR面取り部からなることを特徴とする請求項2に記載の半導体チップの製造方法。3. The method according to claim 2, wherein the re-chamfering includes a vertical portion and an R-chamfered portion.
JP2002274923A 2002-09-20 2002-09-20 Manufacture of semiconductor chip Pending JP2004111799A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007335521A (en) * 2006-06-13 2007-12-27 Tokyo Seimitsu Co Ltd Method for grinding outer periphery of wafer
CN109360852A (en) * 2018-08-14 2019-02-19 上海芯石微电子有限公司 A kind of wafer chamfering structure and method reducing chip thinning fragment rate
CN111952414A (en) * 2020-08-21 2020-11-17 晶科绿能(上海)管理有限公司 Post-cutting passivation method of silicon-based semiconductor device and silicon-based semiconductor device
US12125936B2 (en) 2020-08-21 2024-10-22 Jinko Green Energy (Shanghai) Management Co., LTD Method for passivating silicon-based semiconductor device, and silicon-based semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007335521A (en) * 2006-06-13 2007-12-27 Tokyo Seimitsu Co Ltd Method for grinding outer periphery of wafer
CN109360852A (en) * 2018-08-14 2019-02-19 上海芯石微电子有限公司 A kind of wafer chamfering structure and method reducing chip thinning fragment rate
CN111952414A (en) * 2020-08-21 2020-11-17 晶科绿能(上海)管理有限公司 Post-cutting passivation method of silicon-based semiconductor device and silicon-based semiconductor device
CN111952414B (en) * 2020-08-21 2023-02-28 晶科绿能(上海)管理有限公司 Post-cutting passivation method of silicon-based semiconductor device and silicon-based semiconductor device
US12125936B2 (en) 2020-08-21 2024-10-22 Jinko Green Energy (Shanghai) Management Co., LTD Method for passivating silicon-based semiconductor device, and silicon-based semiconductor device

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