JP2001127010A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of any crack at the bonding part of a semiconductor chip and a dicing tape at the time of adhering the dicing tape on the back face of a semiconductor wafer, and then cutting and separating the semiconductor chip by using a cutting blade. SOLUTION: At the time of cutting and separating a semiconductor wafer on which devices are formed by repeatedly forming shallow grooves by rotating and moving a cutting blade, plural ladder-shaped dicing grooves are formed by successively switching the width of the blades corresponding to the depth of the dicing grooves from the larger width to the smaller width. For example, a first dicing groove 11 whose width is w1 and whose depth is d1 is formed by using a first cutting blade, and a second dicing groove 12 whose width is w2 and whose depth is d2 is formed by using a second cutting blade, and finally a third dicing groove 13 whose width is w3 and whose depth is d3 is formed by using a third cutting blade.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a cross-sectional structure of a thin semiconductor chip used for an IC card or the like and a method of manufacturing a semiconductor device including a dicing process suitable for manufacturing the same. .

[0002]

2. Description of the Related Art FIG. 2A is a sectional view showing a state in which a semiconductor chip is cut and separated from a wafer 22 on which semiconductor devices are formed using a conventional dicing saw type cutting blade. As shown in the figure, the dicing groove 21 formed by the wafer cutting is one step, and the groove width is substantially equal to the width of the cutting blade.

The semiconductor chip 24 thus cut and separated is mounted on a card, and the necessary wiring 25 and coil 26
The IC card 27 shown in the plane of FIG.

[0004] Incidentally, as a technique related to a technique for manufacturing an IC card using a semiconductor chip cut out of this kind of wafer dicing and cut out, for example, Japanese Unexamined Patent Publication No. 7-9926.
No. 7 can be cited.

[0005]

As shown in FIG. 2A,
In the step of cutting and separating the semiconductor chip, a dicing saw method is generally used in which a dicing tape 15 is attached to the back surface of the semiconductor wafer 22 in advance, and then the semiconductor wafer 22 is cut using a cutting blade and cut on the surface of the dicing tape 15. Has been adopted.

When cutting a thin semiconductor wafer used for an IC card or the like, a crack 23 due to a large cutting energy enters a portion where the dicing tape 15 and the semiconductor wafer 22 are bonded, which causes chipping. . That is, energy is concentrated on the portion where the dicing tape 15 and the semiconductor wafer 22 are bonded at the time of cutting and separation, and if the bonding is insufficient, cracks or minute Scratches occur.

These cracks and fine scratches cause chipping in a thin IC card semiconductor chip. When chipping occurs, the die strength of the chip is degraded, and the mechanical strength of the IC card is reduced, thereby significantly reducing the reliability.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned conventional problem of chipping and to provide an improved structure of a cut surface of a semiconductor chip and a method of manufacturing a semiconductor device including the cutting and separating step.

[0009]

Means for Solving the Problems The present inventors conducted various experimental studies to solve this problem, and found that the occurrence of chipping was deeply related to the cutting depth and the dicing groove width. I obtained important knowledge. The present invention has been made based on such knowledge, and is different from the conventional technique in which the dicing groove 21 described in FIG. 2A is a single step, and the groove width is stepwise adjusted according to the cutting depth. In this method, a plurality of steps are formed as a cross-sectional shape of a portion where the semiconductor chip is cut and separated.

Therefore, the feature of the semiconductor device of the present invention formed in this manner is that the peripheral shape of the semiconductor chip corresponds to the structure of the dicing groove for cutting and separating from the wafer. In that it has a multi-stage picture frame-like structure that is gradually expanded toward.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A typical configuration example of the present invention capable of achieving the above object will be described below. A feature of the present invention is a method for manufacturing a semiconductor device including a dicing step of cutting and separating a semiconductor chip from a semiconductor wafer on which devices are formed, wherein the dicing step includes rotating a cutting blade to form a shallow dicing groove. A step of repeatedly forming on a semiconductor wafer, cutting the width of the cutting blade stepwise according to the depth of the dicing groove, and cutting so that the cross-sectional shape of the cut and separated portion forms a plurality of steps. And a step of performing

It is desirable to perform cutting by controlling the positions of the blades so that the center positions of the respective cutting blades always keep the same central axis so as not to be eccentric.

In the present invention, as a step before the dicing step, after forming a device on one main surface of the semiconductor wafer, the back surface is processed to a thickness of 1 to 110 μm by mechanical grinding and etching. Process.

The back surface of the processed semiconductor wafer is mirror-finished, for example, the average surface roughness of the unevenness is 10 μm.
Hereinafter, the thickness is preferably set to 0.5 to 1.5 μm.

In the dicing step, a dicing tape made of an organic polymer film such as vinyl chloride or polyethylene terephthalate (PET) and an adhesive such as an acrylic adhesive are used on the back surface of the mirror-finished wafer. It is enough to adhere.

As described above, if a portion that is insufficient for adhesion occurs, in the dicing step, the portion resonates with the vibration of the blade and causes cracks and fine scratches. Adhering is desirable.

In the dicing step, as described above, the width of the cutting blade is reduced stepwise in accordance with the depth of the dicing groove, and the cross-sectional shape of the cut and separated portion has a plurality of steps. It is important to cut as much as possible, but in order to minimize the occurrence of cracks, it is desirable to cut the dicing groove as shallow as possible in each step and to increase the number of steps.

However, although it is desirable to increase the number of stages, a large number of blades having different widths are required.
In addition, since the processing time becomes longer and the throughput decreases, it is practically desirable to set the number to about 2 to 5 steps.

Hereinafter, a specific description will be given with reference to FIGS. 1, 3 and 4. For example, as shown in FIG. 1, first, a device (IC) is previously formed on a surface to a thickness of 200 to 300 μm.
The sample wafer 14 is a thin wafer having a thickness of 1 to 110 μm, which is obtained by grinding and etching the back surface of a 6 to 8 inch wafer having a thickness of m and mirror finishing. A dicing tape 15 is adhered to the back surface of the mirror-finished sample wafer, and the semiconductor chips 16 are cut and separated in the following dicing process. 1A is a plan view of the wafer, FIG. 1B is a partially enlarged view,
FIG. 1C is a sectional view of a dicing groove.

In this example, the sample wafer 14 has a width w ₁ to
three types of dicing grooves 11 to 11 having w ₃ and depths d ₁ to d ₃
The semiconductor chips 16 are cut and separated by sequentially forming the semiconductor chips 13. However, the _{w 1> w 2> w 3} , d 1 ~d 3 is reference to the cross-sectional area ratio of the dicing groove is determined as dicing energy decreases. For example, the ratio is set such that approximately 1/2 of the blade width is aimed at.

As shown in FIG. 1C, initially, the width w ₁ ,
A first dicing groove 11 having a depth d ₁ is formed. Next, a second dicing groove 12 having a width w ₂ and a depth d ₂ is formed.
Finally, a third dicing groove 13 having a width w ₃ and a depth d ₃ is formed, and the semiconductor chip 16 is cut and separated.

As described above, according to the present invention, when dicing a semiconductor wafer, the dicing energy is reduced by gradually reducing the dicing groove width in accordance with the cutting depth, thereby preventing the occurrence of cracks. When dicing is performed in two or more stages so as to have a step-like shape in comparison with the conventional one-stage dicing, cracks are eliminated. Further, cracks are further reduced by reducing the thickness of the wafer to a thickness of 1 to 110 μm.

Further, since cracks are prevented by improving the adhesiveness between the semiconductor wafer and the dicing tape, the back surface of the semiconductor wafer is finished like a mirror surface by wet etching or dry etching after mechanical grinding. Effective in preventing cracks. The greater the adhesion between the semiconductor wafer and the dicing tape, the fewer cracks. By reducing cracks, chipping of semiconductor chips cut and separated from the wafer can be reduced.

FIG. 3 is a sectional view of a semiconductor chip cut and separated from a wafer by dicing. Steps formed by the traces of the plurality of dicing grooves 11 to 13 formed by the dicing step shown in FIG. The number of steps is three or more, and FIG. 3 shows an example of three steps.

Since the periphery of the chip has a step-like shape, dicing with reduced cracks is performed.
In the completed semiconductor chip 16, a chip with little chipping can be obtained.

The thickness of the semiconductor chip 16 is 1 to 110 μm
It is. This is because the function of the IC card is configured as an integrated circuit in this semiconductor chip,
When incorporated in a plastic plate with a thickness of 0 to 760 μm, the plastic plate is stressed and deformed in various living places. Becomes possible. Further, by making the back surface of the semiconductor chip 16 a mirror finish, it is possible to make the semiconductor chip 16 resistant to stress.

FIG. 4 is a process chart for explaining the dicing process of FIG. 1 more specifically. FIG. 4A shows a cross-sectional view immediately after the step of attaching the semiconductor wafer 14 to the dicing tape 15.

FIG. 4B shows the first blade 41
2 shows a cross-sectional view of the step of dicing. The dicing at this time is not cut completely, but is cut to an intermediate depth to form a first dicing groove having a width w ₁ and a depth d ₁ .

FIG. 4C shows the second blade 42
2 shows a cross-sectional view of the step of dicing. At this time, the dicing is not cut completely, but is cut to an intermediate depth to form a second dicing groove having a width w ₂ and a depth d ₂ . The width of the second blade 42 is smaller than the width of the first blade 41.

FIG. 4 (d) shows the third blade 43
2 shows a cross-sectional view of the step of dicing. At this time, dicing is performed by full cutting to form a second dicing groove having a width w ₂ and a depth d ₂ . The width of the third blade 43 is smaller than the width of the second blade 42.

In the final cutting, the thinned silicon is cut with a narrow blade, so that dicing is performed in a state where the energy is the smallest, so that cracks are not formed, that is, dicing with less chipping becomes possible. Further, if the first silicon is thin, the dicing is performed in a state where the energy is the smallest because the silicon is thin, so that no crack is generated, that is, dicing with less chipping is possible.

FIG. 6 shows the planar shape of the semiconductor chip 14 after the dicing shown in FIG. The first shape 61 from the outside corresponds to the third dicing groove 13 in FIG.
FIG. 4D shows the outer periphery of the third dicing groove processed by the third blade 43 in FIG.

The second shape 62 from the outside is formed by the second dicing groove 12 in FIG. 1 and shows the outer periphery of the second dicing groove processed by the second blade 42 in FIG. 4C. ing.

The third shape 63 from the outside is shown in FIG.
4B shows the outer periphery of the first dicing groove processed by the first blade 41 in FIG. 4B.

As described above, the peripheral shape of the semiconductor chip manufactured according to the present invention is gradually expanded from the main surface on which the device is formed to the outer periphery in accordance with the structure of the dicing groove cut and separated from the wafer. It has a multi-stage frame-like structure.

This planar shape differs depending on the dicing pitch, kerf width and the number of dicing steps. In the present invention, cracks are prevented by the appearance of a plurality of outer peripheries on the outer periphery of the semiconductor chip with the number of dicing steps. It is possible to determine whether dicing has been performed according to the method of the present invention.

Further, by observing the thickness of the semiconductor chip and the surface condition of the back surface, it is possible to confirm whether the semiconductor wafer is strongly bonded and the dicing of the semiconductor wafer is performed with low energy.

[0038]

An embodiment of the present invention will be described below with reference to the drawings. <Embodiment 1> FIG. 7 is a schematic view showing a manufacturing process of a semiconductor device according to the present invention. FIG. 2 is a plan view of an IC card in which an IC chip cut and separated from a wafer in the manufacturing process of FIG. 7 is mounted on an IC card.

Hereinafter, description will be made sequentially according to the process chart of FIG. (1) In the IC forming step 71, a plurality of ICs are formed on a 6-inch Si wafer having a thickness of 200 μm.

(2) In the wafer thinning step 72, the IC
While the surface of the wafer on which is formed is protected, the back surface is formed into a thin film having a thickness of 110 μm through mechanical grinding and etching. The back surface of the processed wafer has a mirror finish with an average roughness of 1 μm.

(3) The dicing step 73 will be specifically described with reference to the step diagrams of FIGS. First, as shown in FIG. 4 (a), a vinyl chloride-based dicing tape is adhered to the back surface of the mirror-finished wafer using an acrylic adhesive, and then a semiconductor dicing machine is used in accordance with the following steps using a commercially available dicing apparatus. The chip (IC chip) 14 is cut and separated. In the dicing apparatus, a cutting blade (diamond blade) is rotated at a high speed of 50,000 revolutions per minute, and the blade is moved along vertical and horizontal cutting lines as shown in FIG. Then, a dicing groove is formed, and each IC chip 14 is cut and separated from the wafer 14.

As shown in FIG. 4B, dicing is performed with the first cutting blade 41 having a width of 40 μm, and the width (w
₁ ) forms a first dicing groove 11 having a thickness of about 50 μm and a depth (d ₁ ) of 25 μm.

As shown in FIG. 4C, dicing is performed with a second blade 42 having a width of 25 μm, and the width (w
₂ ) to form a second dicing groove 12 having a thickness of about 30 μm and a depth (d ₂ ) of 25 μm.

Finally, as shown in FIG.
m is diced with the third blade 43 for cutting,
While forming a dicing groove having a width (w ₃ ) of about 20 μm, the remaining depth (d ₃ ) of 60 μm is cut to cut and separate the IC chip 16. Thus, the IC chip 16 shown in the sectional view of FIG. 3 and the plan view of FIG. 6 was manufactured.

(4) Returning to the description of FIG. In a chip mounting / mounting step 74 on the IC card, the IC chip 16 cut and separated in the above step was mounted on the card and necessary circuit connections were made to form an IC card. FIG. B2 is an external plan view of the IC card.

When the forced life test of the IC card thus obtained is compared with the conventional product (one-stage dicing IC chip), the chipping rate of the semiconductor chip is 1/2 to 1/5 of the conventional product. The reduction was remarkable, and the reliability was remarkably improved.

<Embodiment 2> FIG. 5A shows another embodiment of the present invention. This example is characterized in that dicing is performed in two steps, and the cross-sectional shape of the formed dicing groove is two steps. That is, the structure of the dicing groove has two stages: the first dicing groove 51 and the second dicing groove 52 having a smaller width.

The wafer 14 on which the IC is formed has a thickness of 50 μm.
The thin film having a thickness of m was used as a sample. The back surface of the wafer was mirror-finished as in Example 1, and a dicing tape 15 was stuck thereon. The dicing process is substantially the same as that in FIG. 4 of the first embodiment, but differs in that the sample wafer 14 is made thinner and that the dicing grooves are provided in two stages. Therefore, here, the dicing step for forming the dicing groove of FIG. 5A will be mainly described.

First, dicing is performed with a first cutting blade having a width of 35 μm to form a first dicing groove 51 having a width (w ₁ ) of about 40 μm and a depth (d ₁ ) of 20 μm.

Next, dicing is performed with a second blade for cutting having a width of 15 μm to form a second dicing groove 52 having a width (w ₂ ) of about 20 μm and a remaining depth (d ₂ ) of 30 μm. Cut to separate. Thus, the IC chip shown in the sectional view of FIG. 5A and the plan view of FIG. 6 was manufactured.

Using this IC chip, an IC card was manufactured in the same manner as in Example 1. When the forced life test of the IC card thus obtained is compared with the conventional product (one-stage dicing IC chip), the chipping occurrence rate of the semiconductor chip is remarkably 1/2 to 1/5 of the conventional product. It was able to reduce, and the reliability was remarkably improved.

<Embodiment 3> FIG. 5B shows another embodiment of the present invention. In this example, dicing is 4
It is characterized in that the cross-sectional shape of the dicing groove formed by performing steps is four steps. By increasing the number of steps, the depth of one dicing can be reduced, and cracks in the silicon material during each dicing are reduced. Even if the number of dicing grooves increases, if multiple dicing blades are continuously arranged as a dicing method so that dicing proceeds in one travel operation, it is easy and simple in positioning and processing time. It is possible to finish.

In this example, the wafer 14 on which the IC is formed is
A thin film having a thickness of 40 μm was used as a sample. The back surface of the wafer was mirror-finished as in Example 1, and a dicing tape 15 was stuck thereon. The dicing process is substantially the same as that in FIG. 4 of the first embodiment, but differs in that the sample wafer 14 is made thinner and that the dicing grooves are provided in four stages. Therefore, here, the dicing step for forming the dicing groove shown in FIG. 5B will be mainly described.

First, dicing is performed with a first cutting blade having a width of 40 μm to form a first dicing groove 51 having a width (w ₁ ) of about 50 μm and a depth (d ₁ ) of 10 μm.

Next, dicing is performed with a second blade for cutting having a width of 30 μm to form a second dicing groove 52 having a width (w ₂ ) of about 40 μm and a depth (d ₂ ) of 10 μm.

Further, dicing is performed with a third blade for cutting having a width of 25 μm to form a third dicing groove 53 having a width (w ₃ ) of about 30 μm and a depth (d ₃ ) of 10 μm.

Finally, dicing is performed with a fourth blade for cutting having a width of 15 μm, and a fourth dicing groove 54 having a width (w ₄ ) of about 10 μm and a remaining depth (d ₄ ) of 10 μm is formed. Cut and separate the chip. Thus, the IC chip shown in the sectional view of FIG. 5B and the plan view of FIG. 6 was manufactured.

Using this IC chip, an IC card was manufactured in the same manner as in Example 1. When the forced life test of the IC card thus obtained is compared with the conventional product (one-stage dicing IC chip), the chipping occurrence rate of the semiconductor chip is remarkably 1/3 to 1/5 of the conventional product. It was able to reduce, and the reliability was remarkably improved.

[0059]

As described in detail above, the present invention has achieved the intended object of the present invention, which is to solve the conventional problem of chipping. When an IC card is formed by using a semiconductor chip manufactured according to the present invention, cracking of the semiconductor chip is significantly reduced, so that chipping is suppressed, and the IC is formed without deteriorating the die strength of the chip. The mechanical strength of the card can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a dicing groove according to an embodiment of the present invention and a plan view illustrating a dicing step.

FIG. 2A is a cross section of a dicing groove as a conventional example.

FIG. 2B is a plan view of an IC chip.

FIG. 3 is a sectional view of a semiconductor chip according to one embodiment of the present invention.

FIG. 4 is a sectional view showing a dicing step according to an embodiment of the present invention.

FIG. 5A is a cross section of a dicing groove according to another embodiment of the present invention.

FIG. 5B is a cross section of a dicing groove according to another embodiment of the present invention.

FIG. 6 is a plan view of a semiconductor chip according to one embodiment of the present invention.

FIG. 7 is an explanatory diagram of a dicing step.

[Explanation of symbols]

11: first dicing groove, 12: second dicing groove, 13: third dicing groove,
14: semiconductor wafer, 15: dicing tape,
16: semiconductor chip, 21: dicing groove,
22 semiconductor wafer, 23 crack, 24 semiconductor chip (IC
Chip), 25 ... wiring, 2
6 ... coil, 27 ... IC card,
41 ... first blade, 42 ... second blade,
43: third blade, 51: one-step dicing groove, 52: two-step dicing groove, 53:
Three-stage dicing groove, 54: Four-stage dicing groove, 61: Outer periphery of third dicing groove, 62:
The outer periphery of the second dicing grooves, 63 ... outer periphery of the first dicing grooves, w ₁ to w ₄ ... dicing groove width, d ₁ to d ₄ ... dicing groove depth.

Claims (10)

[Claims] 1. A multi-stage frame-like structure in which a peripheral shape of a semiconductor chip is stepwise extended from a main surface on which devices are formed to an outer periphery corresponding to a dicing groove structure for cutting and separating from a wafer. A semiconductor device, comprising: 2. A method for manufacturing a semiconductor device, comprising a dicing step of cutting and separating a semiconductor chip from a semiconductor wafer on which devices are formed, wherein the dicing step is performed by rotating a cutting blade to repeatedly form shallow dicing grooves. A step of forming on a semiconductor wafer, and stepwise reducing the width of the cutting blade in accordance with the depth of the dicing groove, and cutting so that the cross-sectional shape of the cut and separated portion forms a plurality of steps. And a method of manufacturing a semiconductor device. 3. The step of reducing the width of the cutting blade in a stepwise manner corresponding to the depth of the dicing groove, and cutting the cross-section of the cut and separated portion so as to form a plurality of steps. Using a plurality of cutting blades having different widths stepwise in order from the widest one to the narrowest one as the cutting blades, aligning the center axis of each cutting blade on the same axis, the cross-sectional shape of the dicing groove is wide 3. The method for manufacturing a semiconductor device according to claim 2, further comprising a step of forming the semiconductor device in a stepwise manner so as to gradually change from a width to a narrow width. 4. The method according to claim 2, further comprising the step of reducing the thickness of the semiconductor wafer on which the devices are formed to a thickness of 1 to 110 μm. 5. The semiconductor device according to claim 4, wherein a back surface of the semiconductor wafer thinned by the thinning step is mirror-finished, and a dicing tape is adhered thereon with an adhesive. Production method. 6. The method of manufacturing a semiconductor device according to claim 5, wherein said thinning step includes a processing step by mechanical grinding and a mirror processing step by etching. 7. The method according to claim 5, wherein said dicing tape is an organic polymer film. 8. The method of manufacturing a semiconductor device according to claim 5, wherein said dicing tape is adhered to the back surface of said wafer by an acrylic adhesive. 9. The method of manufacturing a semiconductor device according to claim 6, wherein the mirror surface processing step by etching is performed to reduce the average surface roughness to 10 μm or less. 10. An IC in which an IC chip is mounted on a card.
An IC card, wherein the IC chip is constituted by the semiconductor device according to claim 1.