JPH0837169A - Method and apparatus for grinding semiconductor substrate and manufacture of semiconductor device - Google Patents

Method and apparatus for grinding semiconductor substrate and manufacture of semiconductor device

Info

Publication number
JPH0837169A
JPH0837169A JP17384994A JP17384994A JPH0837169A JP H0837169 A JPH0837169 A JP H0837169A JP 17384994 A JP17384994 A JP 17384994A JP 17384994 A JP17384994 A JP 17384994A JP H0837169 A JPH0837169 A JP H0837169A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
grinding
back surface
ground
peripheral edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17384994A
Other languages
Japanese (ja)
Inventor
Yoshikatsu Katou
好活 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Hitachi Hokkai Semiconductor Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Hokkai Semiconductor Ltd, Hitachi Ltd filed Critical Hitachi Hokkai Semiconductor Ltd
Priority to JP17384994A priority Critical patent/JPH0837169A/en
Publication of JPH0837169A publication Critical patent/JPH0837169A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the peripheral edge part of a semiconductor substrate from being chipped and cracked and to enhance the yield in a rear grinding process when the rear of the semiconductor substrate is ground. CONSTITUTION:In a state that a semiconductor substrate 1 has been ground to a desired thickness, the semiconductor substrate 1 is tilted with reference to its rear, and its peripheral edge part on the rear is ground so as to become a state that the peripheral edge of the substrate 1 is chamfered. After that, the whole rear of the semiconductor substrate 1 is ground equally in such a way that a part of a slope 1a formed by its grinding operation is left. Consequently, the peripheral edge part on the rear side of the semiconductor substrate 1 is ground while it is tilted with reference to the rear. After that, while the slope 1a at the peripheral edge part on the rear side is left, the rear is ground equally. Thereby, the slope 1a, at the peripheral edge part on the rear side, which is left after the rear has been ground becomes a chamfered shape. As a result, it is possible to prevent the peripheral edge part from being chipped and cracked.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置製造分野に
関するものであり、特に、半導体基板の裏面を研削する
方法に利用して有効なものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor device manufacturing, and is particularly effective when applied to a method of grinding the back surface of a semiconductor substrate.

【0002】[0002]

【従来の技術】トランジスタや半導体集積回路(IC)
のような半導体装置の製造において、半導体基板の主表
面に素子を形成するために、半導体基板表面に不純物注
入、拡散、ホトリソグラフィ、エッチング、CVD等の
処理を施している。この際に、半導体基板を各処理の工
程間で移載、搬送しているため、半導体基板の周縁部に
チッピングが発生し、その破片が半導体基板表面に付着
するという問題があった。この問題を解決するために、
従来は特公昭53−38594号公報に開示されている
ように、半導体基板の周縁部に面取りを施すことが行わ
れている(図7(a))。また最近は、半導体基板の口
径が6インチ、あるいは8インチと大口径化しており、
その強度を維持するために板厚を従来のものより、厚く
することでチッピングや割れを防止している。ところ
が、パッケージにペレットを封止する際、パッケージ厚
が規格化されているため、あらかじめ半導体基板の板厚
を400〜500μm程度に薄くしておく必要がある。
その中でも特にICカードや面実装型のICにおいて
は、板厚を200〜300μm程度まで薄くして、ペレ
ットに分割することが必須となっている。
2. Description of the Related Art Transistors and semiconductor integrated circuits (ICs)
In the manufacture of such a semiconductor device, in order to form an element on the main surface of the semiconductor substrate, the surface of the semiconductor substrate is subjected to treatments such as impurity implantation, diffusion, photolithography, etching and CVD. At this time, since the semiconductor substrate is transferred and transported between each processing step, there is a problem that chipping occurs at the peripheral edge of the semiconductor substrate and the fragments adhere to the surface of the semiconductor substrate. to solve this problem,
Conventionally, as disclosed in JP-B-53-38594, chamfering is performed on the peripheral edge of a semiconductor substrate (FIG. 7A). Recently, the diameter of the semiconductor substrate has been increased to 6 inches or 8 inches,
In order to maintain its strength, the plate thickness is made thicker than the conventional one to prevent chipping and cracking. However, since the package thickness is standardized when the pellets are sealed in the package, it is necessary to reduce the thickness of the semiconductor substrate to about 400 to 500 μm in advance.
Among them, particularly in IC cards and surface mount ICs, it is essential to reduce the plate thickness to about 200 to 300 μm and divide into pellets.

【0003】半導体基板を薄くする技術として、半導体
基板の裏面を機械的に研削する方法が広く用いられてい
る。尚、半導体基板の研削方法については、例えば特公
昭63−12741号公報等に記載されている。
As a technique for thinning a semiconductor substrate, a method of mechanically grinding the back surface of the semiconductor substrate is widely used. The method for grinding a semiconductor substrate is described in, for example, Japanese Patent Publication No. 63-12741.

【0004】[0004]

【発明が解決しようとする課題】半導体基板の裏面を研
削する際、表面に形成された素子を保護するためにレジ
ストまたはテープ等の保護膜を形成させた後に、パッケ
ージ仕様によって規定された厚さまで裏面を研削する
が、裏面研削を行うことにより、半導体基板周縁部の面
取りの断面形状は、図7(b)及び(c)に示すような
鋭角形状に変化する。この形状は、裏面研削する半導体
基板の厚さによって大きく異なり、薄くなるに従い、よ
り鋭角形状になる。さらに半導体基板が薄くなると、基
板自体の強度も極端に低下してしまう。特に最近の大口
径化した半導体基板については、強度の低下が著しい。
よって、鋭角部17bに裏面研削中のストレス、または
後処理工程での衝撃がわずかでも加わると、簡単にチッ
ピングが発生していた。更に、チッピング個所が切れ目
となり、わずかな衝撃で割れやすくなってしまう。
When a back surface of a semiconductor substrate is ground, a protective film such as a resist or a tape is formed in order to protect elements formed on the front surface, and then a thickness specified by package specifications is reached. The back surface is ground, but by carrying out the back surface grinding, the cross-sectional shape of the chamfer of the peripheral edge of the semiconductor substrate changes to an acute angle shape as shown in FIGS. 7B and 7C. This shape greatly differs depending on the thickness of the semiconductor substrate to be ground on the back surface, and becomes thinner as it becomes thinner. Further, if the semiconductor substrate becomes thinner, the strength of the substrate itself will be extremely reduced. In particular, in recent semiconductor substrates having a large diameter, the strength is remarkably reduced.
Therefore, when the acute angle portion 17b is subjected to stress during back surface grinding or even a slight impact in the post-treatment process, chipping easily occurs. Furthermore, the chipping point becomes a break, and it is easy to break with a slight impact.

【0005】そこで、本発明の目的は、半導体基板の裏
面研削に際し、半導体基板周縁部のチッピングや割れを
防止し、裏面研削工程での歩留を向上させることにあ
る。
Therefore, an object of the present invention is to prevent chipping or cracking of the peripheral edge of the semiconductor substrate during backside grinding of the semiconductor substrate and improve the yield in the backside grinding process.

【0006】本発明の前記並びにその他の目的と新規な
特徴は、本明細書の記述及び添付図面から明らかになる
であろう。
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【0007】[0007]

【課題を解決するための手段】本願において開示される
発明のうち代表的なものの概要を簡単に説明すれば、次
のとおりである。すなわち、半導体基板の裏面側の周縁
部を、裏面に対し傾斜させて研削した後、裏面側の周縁
部の傾斜面を残存させながら、裏面の全面を研削するこ
とにより前記半導体基板を所望の厚さにするものであ
る。
The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, after the peripheral edge portion on the back surface side of the semiconductor substrate is inclined and ground with respect to the rear surface, the entire rear surface surface is ground while leaving the inclined surface of the peripheral edge portion on the rear surface side to a desired thickness. It's something to say.

【0008】[0008]

【作用】上記手段によると、裏面研削後残存した裏面側
の周縁部の傾斜面が、面取り形状となるため、チッピン
グや割れを防止することができる。
According to the above means, since the inclined surface of the peripheral portion on the back surface side remaining after grinding the back surface has a chamfered shape, chipping and cracking can be prevented.

【0009】[0009]

【実施例1】以下、本発明の一実施例を図面を用いて説
明する。図1に本発明の半導体装置の製造フロー図、図
2に半導体基板1の研削方法を示す。まず、予め周縁部
が面取りされている半導体基板1の表面に、不純物注
入、拡散、ホトリソグラフィ、エッチング、CVD等の
処理を施すことにより、集積回路を構成する素子を形成
する。次に、半導体基板1表面に形成された素子を保護
するためにレジストまたはテープ等の保護膜を形成し、
研削装置を用いて半導体基板の裏面研削を行う。この
際、半導体基板1を所望の厚さに研削した状態で、半導
体基板1の周縁部が面取りされた状態になるように、裏
面に対し傾斜させて半導体基板1の裏面周縁部を研削す
る。その後、この研削によって形成される傾斜面1aの
一部が残存するように、半導体基板1の裏面全面を均等
に研削する。この方法によると、予め半導体基板1の裏
面周縁部に傾斜面1aを形成しておくので、裏面研削後
も面取りされた状態となっている。従って、裏面研削中
及びその後の後処理工程において、チッピングやそれに
伴う割れを減少させることができる。尚、傾斜面1aを
素子形成前、例えば半導体基板自体を形成する際に、裏
面側に形成しておくと、素子形成後、従来通り裏面研削
のみ行えばよい。
Embodiment 1 An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a manufacturing flow chart of a semiconductor device of the present invention, and FIG. 2 shows a grinding method of a semiconductor substrate 1. First, the surface of the semiconductor substrate 1 whose peripheral edge is chamfered in advance is subjected to treatments such as impurity implantation, diffusion, photolithography, etching and CVD to form an element that constitutes an integrated circuit. Next, a protective film such as a resist or a tape is formed to protect the elements formed on the surface of the semiconductor substrate 1,
The back surface of the semiconductor substrate is ground using a grinding machine. At this time, in the state where the semiconductor substrate 1 is ground to a desired thickness, the rear surface peripheral portion of the semiconductor substrate 1 is ground by inclining it with respect to the rear surface so that the peripheral portion of the semiconductor substrate 1 is chamfered. After that, the entire back surface of the semiconductor substrate 1 is evenly ground so that a part of the inclined surface 1a formed by this grinding remains. According to this method, since the inclined surface 1a is formed in the peripheral portion of the back surface of the semiconductor substrate 1 in advance, it is chamfered even after the back surface is ground. Therefore, chipping and cracks accompanying it can be reduced during back surface grinding and in the subsequent post-treatment process. If the inclined surface 1a is formed on the back surface side before the element is formed, for example, when the semiconductor substrate itself is formed, only the back surface grinding may be performed after the element formation as usual.

【0010】裏面研削を終了した半導体基板1は、洗浄
後、プローブ検査、ダイシング、組立、パッケージング
等の工程を経て、個々の半導体装置に加工される。尚、
洗浄後、薄くなった半導体基板1を補強するために、裏
面からUVテープ等の補強材を張付けてもよい。その場
合は、ダイシング工程まで張付けておき、ペレットのピ
ックアップ時に補強材から剥がすと、裏面研削した薄さ
でペレット取付け基板にマウントすることができる。
After cleaning the back surface, the semiconductor substrate 1 is processed into individual semiconductor devices through steps such as probe inspection, dicing, assembly and packaging after cleaning. still,
After cleaning, in order to reinforce the thinned semiconductor substrate 1, a reinforcing material such as a UV tape may be attached from the back surface. In that case, if the pellets are attached up to the dicing step and peeled off from the reinforcing material when the pellets are picked up, the pellets can be mounted on the pellet mounting substrate with the back surface ground thinness.

【0011】次に、本発明に用いる半導体基板の研削装
置について説明する。図3に研削装置3の主要部を示
す。研削装置3の主要部は、半導体基板1を載置、固定
し、研削の際回転運動を行うステージ4と、円盤上の支
持体6の表面に砥石5が取り付けられ、上下動及び回転
動作が可能な研削部材7から構成される。本発明では、
ステージ4に傾きθを加えることにより、半導体基板1
の裏面周縁部に傾斜部1aを形成することを可能として
いる。まず、半導体基板1を表面を載置面としてステー
ジ4に固定する。次に、ステージ4をθ傾けて回転させ
るとともに、研削部材7を回転させながら下降させて半
導体基板1の周縁部を研削していく。このような研削方
法で傾斜部1aが形成された後、ステージ4を支持体6
の表面に平行な状態に戻し、傾斜部1aを残存させなが
ら半導体基板1の裏面を均等に研削する。この研削装置
3は、ステージ4を傾けるだけで傾斜面1aを形成でき
るため、機構面で大幅な改造を必要としない。従って、
簡単に本発明の裏面研削に対応することができる。
Next, a semiconductor substrate grinding apparatus used in the present invention will be described. FIG. 3 shows the main part of the grinding device 3. The main part of the grinding device 3 is a stage 4 for mounting and fixing the semiconductor substrate 1 and performing a rotary motion at the time of grinding, and a grindstone 5 is attached to the surface of a support 6 on a disk, so that vertical movement and rotary motion can be performed. Composed of possible grinding members 7. In the present invention,
By adding the inclination θ to the stage 4, the semiconductor substrate 1
It is possible to form the inclined portion 1a at the peripheral portion of the back surface of the. First, the semiconductor substrate 1 is fixed to the stage 4 with the front surface as a mounting surface. Next, the stage 4 is rotated with an inclination of θ, and the grinding member 7 is lowered while being rotated to grind the peripheral portion of the semiconductor substrate 1. After the inclined portion 1a is formed by such a grinding method, the stage 4 is attached to the support 6
Then, the back surface of the semiconductor substrate 1 is evenly ground while the inclined portion 1a remains. In this grinding device 3, the inclined surface 1a can be formed only by inclining the stage 4, so that the mechanical surface does not need to be significantly modified. Therefore,
The backside grinding of the present invention can be easily supported.

【0012】[0012]

【実施例2】本実施例では、面取り処理と裏面研削を同
時に行う方法について説明する。図4に本実施例での半
導体装置の製造フロー図、図5に半導体基板8の研削方
法を示す。まず、予め周縁部が面取りされている半導体
基板8の表面に、不純物注入、拡散、ホトリソグラフ
ィ、エッチング、CVD等の処理を施すことにより、集
積回路を構成する素子を形成する。次に、半導体基板8
表面に形成された素子を保護するためにレジストまたは
テープ等の保護膜9を形成し、研削装置を用いて半導体
基板の裏面研削を行う。本実施例では、半導体基板8を
所望の厚さに研削した状態で、半導体基板8の周縁部が
面取りされた状態になるように、裏面研削と同時に裏面
周縁部の面取りを行う。図6に、本実施例に用いる研削
装置10の主要部を示す。研削装置10の主要部は、半
導体基板8を載置、固定し、研削の際回転運動を行うス
テージ11と、円盤上の支持体12の表面に砥石13が
取り付けられ、上下動及び回転動作が可能な研削部材1
4から構成される。本発明では、研削部材14による裏
面研削と同時に周縁部の面取りを行う面取り用砥石16
を設けている。まず、半導体基板8を表面を載置面とし
てステージ11に固定する。次に、研削部材14を回転
させながら下降させて半導体基板8の裏面を均等に研削
するとともに、面取り用砥石16を回転させながら半導
体基板8の裏面側周縁部へ接触させて面取りを行う。こ
の方法により、裏面研削中及びその後の後処理工程にお
いて、チッピングやそれに伴う割れを減少させることが
できるとともに、従来の裏面研削時間内で、半導体基板
の裏面研削と面取りとを両方行うことができる。
[Embodiment 2] In this embodiment, a method for simultaneously performing chamfering and back grinding will be described. FIG. 4 shows a flow chart of manufacturing a semiconductor device in this embodiment, and FIG. 5 shows a method of grinding the semiconductor substrate 8. First, the surface of the semiconductor substrate 8 whose peripheral edge is chamfered in advance is subjected to treatments such as impurity implantation, diffusion, photolithography, etching, and CVD to form an element forming an integrated circuit. Next, the semiconductor substrate 8
A protective film 9 such as a resist or a tape is formed to protect the element formed on the front surface, and the back surface of the semiconductor substrate is ground using a grinding machine. In this embodiment, in the state where the semiconductor substrate 8 is ground to a desired thickness, the back surface is chamfered at the same time as the back surface grinding so that the peripheral portion of the semiconductor substrate 8 is chamfered. FIG. 6 shows a main part of the grinding device 10 used in this embodiment. The main part of the grinding apparatus 10 is a stage 11 that mounts and fixes the semiconductor substrate 8 and performs a rotary motion during grinding, and a grindstone 13 is attached to the surface of a support 12 on a disk so that vertical movement and rotation can be performed. Possible grinding member 1
It is composed of 4. In the present invention, the chamfering grindstone 16 for chamfering the peripheral portion simultaneously with the back surface grinding by the grinding member 14
Is provided. First, the semiconductor substrate 8 is fixed to the stage 11 with the front surface as a mounting surface. Next, the grinding member 14 is rotated and lowered to uniformly grind the back surface of the semiconductor substrate 8, and the chamfering grindstone 16 is rotated to be brought into contact with the peripheral edge portion on the back surface side of the semiconductor substrate 8 for chamfering. By this method, chipping and cracks accompanying it can be reduced during the backside grinding and the subsequent post-treatment step, and both the backside grinding and the chamfering of the semiconductor substrate can be performed within the conventional backside grinding time. .

【0013】裏面研削を終了した半導体基板8は、洗浄
後、プローブ検査、ダイシング、組立、パッケージング
等の工程を経て、個々の半導体装置に加工される。
After cleaning the back surface of the semiconductor substrate 8, the semiconductor substrate 8 is processed into individual semiconductor devices through steps such as probe inspection, dicing, assembly and packaging.

【0014】以下、本発明の作用効果について説明す
る。
The operation and effect of the present invention will be described below.

【0015】(1)半導体基板の裏面側の周縁部を、裏
面に対し傾斜させて研削した後、裏面側の周縁部の傾斜
面を残存させながら、裏面を均等に研削することによ
り、裏面研削後残存した裏面側の周縁部の傾斜面が、面
取り形状となるため、チッピングや割れを防止すること
ができる。
(1) The back surface is ground by inclining the peripheral edge portion on the back surface side of the semiconductor substrate with respect to the back surface and then grinding the back surface evenly while leaving the inclined surface of the peripheral edge portion on the back surface side. Since the inclined surface of the peripheral portion on the back surface side that remains afterward has a chamfered shape, chipping and cracking can be prevented.

【0016】(2)予め周縁部が面取り処理されている
半導体基板の裏面側の周縁部を、裏面に対し傾斜させて
研削した後、裏面側の周縁部の傾斜面を残存させなが
ら、裏面を均等に研削するので、表面側の面取りを新た
に行わなくてもよい。
(2) After grinding the backside peripheral edge of the semiconductor substrate whose peripheral edge has been chamfered in advance with respect to the backside, grinding the backside while leaving the backside peripheral edge sloped surface. Since the grinding is performed uniformly, it is not necessary to newly chamfer the front surface side.

【0017】(3)裏面側の周縁部の傾斜面を、半導体
基板へ素子を形成する前に形成しておくことにより、素
子形成後、従来通り裏面研削のみを行うことができる。
(3) By forming the inclined surface of the peripheral portion on the back surface side before forming the element on the semiconductor substrate, only the back surface grinding can be performed after the element formation as usual.

【0018】(4)半導体基板の裏面を研削すると同時
に、裏面側の周縁部を面取り処理することにより、裏面
研削中及びその後の後処理工程において、チッピングや
それに伴う割れを減少させることができるとともに、従
来の裏面研削時間内で、半導体基板の裏面研削と面取り
とを両方行うことができる。
(4) By grinding the back surface of the semiconductor substrate and chamfering the peripheral portion on the back surface side at the same time, chipping and accompanying cracks can be reduced during the back surface grinding and in the subsequent post-processing steps. Both the back surface grinding and the chamfering of the semiconductor substrate can be performed within the conventional back surface grinding time.

【0019】(5)研削装置を、ステージまたは研削部
材に傾きを加えた状態で研削可能としたので、研削装置
に新たに研削部材を追加せずに半導体基板の裏面側の周
縁部を、裏面に対し傾斜させて研削することができる。
(5) Since the grinding device can grind in a state in which the stage or the grinding member is tilted, the peripheral portion on the back surface side of the semiconductor substrate can be changed to the back surface without adding a new grinding member to the grinding device. It can be inclined and ground.

【0020】(6)半導体装置の製造方法に、半導体基
板の裏面側の周縁部を、裏面に対し傾斜させて研削した
後、裏面側の周縁部の傾斜面を残存させながら、裏面を
均等に研削する工程を具備することにより、薄型パッケ
ージのICやICカードの製造歩留を向上させることが
できる。
(6) In the method of manufacturing a semiconductor device, the peripheral portion of the back surface side of the semiconductor substrate is inclined and ground with respect to the rear surface, and then the inclined surface of the peripheral edge portion of the rear surface side is left and the rear surface is evenly formed. By including the step of grinding, it is possible to improve the manufacturing yield of thin package ICs and IC cards.

【0021】[0021]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。
The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

【0022】すなわち、半導体基板の裏面側の周縁部
を、裏面に対し傾斜させて研削した後、裏面側の周縁部
の傾斜面を残存させながら、裏面を均等に研削すること
により、裏面研削後残存した裏面側の周縁部の傾斜面
が、面取り形状となるため、チッピングや割れを防止す
ることができる。
That is, after grinding the back surface side peripheral edge of the semiconductor substrate while inclining to the back surface, the back surface is evenly ground while leaving the inclined surface of the back surface side peripheral edge part, and after the back surface grinding. Since the remaining inclined surface of the peripheral portion on the back surface side has a chamfered shape, chipping and cracking can be prevented.

【0023】[0023]

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例である半導体装置の製造方法
の製造フロー図である。
FIG. 1 is a manufacturing flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

【図2】(a)は、面取り処理された半導体基板の断面
を示す。(b)は、半導体基板の裏面周縁部に傾斜面を
形成した状態の断面図である。(c)は、傾斜面を一部
残存させて、半導体基板の裏面を均等に研削した状態の
断面図を示す。
FIG. 2A shows a cross section of a chamfered semiconductor substrate. FIG. 3B is a sectional view showing a state in which an inclined surface is formed at the peripheral edge of the back surface of the semiconductor substrate. (C) shows a cross-sectional view of a state in which the back surface of the semiconductor substrate is evenly ground with a part of the inclined surface remaining.

【図3】本発明の一実施例である研削装置の主要部を示
す図である。
FIG. 3 is a diagram showing a main part of a grinding apparatus that is an embodiment of the present invention.

【図4】本発明の他の実施例である半導体装置の製造方
法の製造フロー図である。
FIG. 4 is a manufacturing flow chart of a method of manufacturing a semiconductor device according to another embodiment of the present invention.

【図5】(a)は、面取りされた半導体基板の断面を示
す。(b)は、裏面研削と同時に面取り処理を施した状
態の半導体基板の断面図である。
FIG. 5A shows a cross section of a chamfered semiconductor substrate. (B) is a cross-sectional view of the semiconductor substrate in a state where a chamfering process is performed simultaneously with the back surface grinding.

【図6】本発明の他の実施例である研削装置の主要部を
示す図である。
FIG. 6 is a diagram showing a main part of a grinding apparatus that is another embodiment of the present invention.

【図7】(a)は、面取り処理された半導体基板の断面
を示す。(b)は、従来の裏面研削の状態を示す半導体
基板の断面図である。(c)は、(b)の半導体基板の
周縁部の拡大図である。
FIG. 7A shows a cross section of a chamfered semiconductor substrate. FIG. 6B is a cross-sectional view of the semiconductor substrate showing a state of conventional backside grinding. (C) is an enlarged view of the peripheral portion of the semiconductor substrate of (b).

【符号の説明】[Explanation of symbols]

1……半導体基板,1a……傾斜面,2……保護膜,3
……研削装置,4……ステージ,5……砥石,6……支
持体,7……研削部材,8……半導体基板,9……保護
膜,10……研削装置,11……ステージ,12……支
持部材,13……砥石,14……研削部材,15……ス
ピンドル,16……面取り用砥石,17……半導体基
板,17a……研削面,17b……鋭角部,18……保
護膜
1 ... Semiconductor substrate, 1a ... Inclined surface, 2 ... Protective film, 3
…… Grinding device, 4 …… Stage, 5 …… Grinding stone, 6 …… Supporting body, 7 …… Grinding member, 8 …… Semiconductor substrate, 9 …… Protective film, 10 …… Grinding device, 11 …… Stage, 12 ... Support member, 13 ... Grinding stone, 14 ... Grinding member, 15 ... Spindle, 16 ... Chamfering grindstone, 17 ... Semiconductor substrate, 17a ... Grinding surface, 17b ... Sharp corner, 18 ... Protective film

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】半導体基板の裏面全面を研削し、板厚を薄
くする半導体基板の研削方法であって、前記半導体基板
の裏面側の周縁部を、前記裏面に対し傾斜させて研削し
た後、前記裏面側の周縁部の傾斜面を残存させながら、
前記裏面を均等に研削することにより前記半導体基板を
所望の厚さにすることを特徴とする半導体基板の研削方
法。
1. A method of grinding a semiconductor substrate, wherein the entire back surface of a semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, the peripheral edge portion of the semiconductor substrate on the back surface side being inclined with respect to the back surface, and then ground. While leaving the inclined surface of the peripheral portion on the back surface side,
A method of grinding a semiconductor substrate, wherein the semiconductor substrate is made to have a desired thickness by uniformly grinding the back surface.
【請求項2】前記半導体基板は、予め周縁部が面取り処
理されていることを特徴とする請求項1記載の半導体基
板の研削方法。
2. The method for grinding a semiconductor substrate according to claim 1, wherein the peripheral edge portion of the semiconductor substrate is chamfered in advance.
【請求項3】前記裏面側の周縁部の傾斜面は、前記半導
体基板へ素子を形成する前に形成しておくことを特徴と
する請求項1又は2記載の半導体基板の研削方法。
3. The method of grinding a semiconductor substrate according to claim 1, wherein the inclined surface of the peripheral portion on the back surface side is formed before forming an element on the semiconductor substrate.
【請求項4】半導体基板の裏面全面を研削し、板厚を薄
くする半導体基板の研削方法であって、前記半導体基板
の裏面を研削すると同時に、裏面側の周縁部を面取り処
理することを特徴とする半導体基板の研削方法。
4. A method of grinding a semiconductor substrate, wherein the entire back surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, wherein the back surface of the semiconductor substrate is ground and the peripheral portion of the back surface side is chamfered. And a method for grinding a semiconductor substrate.
【請求項5】半導体基板を固定し回転動作を行うステー
ジと、円盤上の支持体の表面に砥石が取り付けられ、前
記ステージに平行な状態で回転動作することにより前記
半導体基板の研削面を研削する研削部材とから構成され
る研削装置であって、前記ステージまたは前記研削部材
に傾きを加えた状態で研削可能な研削装置。
5. A stage for fixing and rotating a semiconductor substrate, and a grindstone attached to the surface of a support on a disk. The grinding face of the semiconductor substrate is ground by rotating in parallel with the stage. A grinding device configured to grind in a state in which the stage or the grinding member is tilted.
【請求項6】請求項1乃至3のいずれか1項に記載の半
導体基板の研削方法を備えたことを特徴とする半導体装
置の製造方法。
6. A method of manufacturing a semiconductor device, comprising the method of grinding a semiconductor substrate according to claim 1.
JP17384994A 1994-07-26 1994-07-26 Method and apparatus for grinding semiconductor substrate and manufacture of semiconductor device Pending JPH0837169A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17384994A JPH0837169A (en) 1994-07-26 1994-07-26 Method and apparatus for grinding semiconductor substrate and manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17384994A JPH0837169A (en) 1994-07-26 1994-07-26 Method and apparatus for grinding semiconductor substrate and manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0837169A true JPH0837169A (en) 1996-02-06

Family

ID=15968300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17384994A Pending JPH0837169A (en) 1994-07-26 1994-07-26 Method and apparatus for grinding semiconductor substrate and manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0837169A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0971398A1 (en) * 1998-07-08 2000-01-12 Shin-Etsu Handotai Co., Ltd. Manufacturing process for semiconductor wafer
EP1484792A1 (en) * 2002-03-14 2004-12-08 Disco Corporation Method for grinding rear surface of semiconductor wafer
US6930023B2 (en) 2000-05-16 2005-08-16 Shin-Etsu Handotai Co, Ltd. Semiconductor wafer thinning method, and thin semiconductor wafer
WO2011161906A1 (en) * 2010-06-21 2011-12-29 三菱電機株式会社 Method and device for producing silicon carbide semiconductor element
JP2013131588A (en) * 2011-12-21 2013-07-04 Mitsubishi Electric Corp Wafer manufacturing method and semiconductor device manufacturing method
JP2014027000A (en) * 2012-07-24 2014-02-06 Disco Abrasive Syst Ltd Grinding device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0971398A1 (en) * 1998-07-08 2000-01-12 Shin-Etsu Handotai Co., Ltd. Manufacturing process for semiconductor wafer
US6930023B2 (en) 2000-05-16 2005-08-16 Shin-Etsu Handotai Co, Ltd. Semiconductor wafer thinning method, and thin semiconductor wafer
EP1484792A1 (en) * 2002-03-14 2004-12-08 Disco Corporation Method for grinding rear surface of semiconductor wafer
EP1484792A4 (en) * 2002-03-14 2006-08-02 Disco Corp Method for grinding rear surface of semiconductor wafer
WO2011161906A1 (en) * 2010-06-21 2011-12-29 三菱電機株式会社 Method and device for producing silicon carbide semiconductor element
JPWO2011161906A1 (en) * 2010-06-21 2013-08-19 三菱電機株式会社 Method and apparatus for manufacturing silicon carbide semiconductor element
JP2013131588A (en) * 2011-12-21 2013-07-04 Mitsubishi Electric Corp Wafer manufacturing method and semiconductor device manufacturing method
JP2014027000A (en) * 2012-07-24 2014-02-06 Disco Abrasive Syst Ltd Grinding device

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