DE60100779T2 - Halbleiteranordnung mit einer unkomplizierten Schnittstelle sowie einer logischen Schaltung und einer eingebauten Speicheranordnung - Google Patents

Halbleiteranordnung mit einer unkomplizierten Schnittstelle sowie einer logischen Schaltung und einer eingebauten Speicheranordnung Download PDF

Info

Publication number
DE60100779T2
DE60100779T2 DE60100779T DE60100779T DE60100779T2 DE 60100779 T2 DE60100779 T2 DE 60100779T2 DE 60100779 T DE60100779 T DE 60100779T DE 60100779 T DE60100779 T DE 60100779T DE 60100779 T2 DE60100779 T2 DE 60100779T2
Authority
DE
Germany
Prior art keywords
data
register
signal
logic
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60100779T
Other languages
German (de)
English (en)
Other versions
DE60100779D1 (de
Inventor
Tadaaki Yamauchi
Kunihiko Kozaru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of DE60100779D1 publication Critical patent/DE60100779D1/de
Publication of DE60100779T2 publication Critical patent/DE60100779T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Storage Device Security (AREA)
  • Memory System (AREA)
DE60100779T 2000-09-29 2001-07-25 Halbleiteranordnung mit einer unkomplizierten Schnittstelle sowie einer logischen Schaltung und einer eingebauten Speicheranordnung Expired - Lifetime DE60100779T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2000299384 2000-09-29
JP2000299384 2000-09-29
JP2000374153 2000-12-08
JP2000374153A JP2002175689A (ja) 2000-09-29 2000-12-08 半導体集積回路装置

Publications (2)

Publication Number Publication Date
DE60100779D1 DE60100779D1 (de) 2003-10-23
DE60100779T2 true DE60100779T2 (de) 2004-07-15

Family

ID=26601155

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60100779T Expired - Lifetime DE60100779T2 (de) 2000-09-29 2001-07-25 Halbleiteranordnung mit einer unkomplizierten Schnittstelle sowie einer logischen Schaltung und einer eingebauten Speicheranordnung

Country Status (6)

Country Link
US (1) US6728827B2 (enExample)
EP (1) EP1199724B1 (enExample)
JP (1) JP2002175689A (enExample)
KR (1) KR100422490B1 (enExample)
DE (1) DE60100779T2 (enExample)
TW (1) TW521276B (enExample)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4890737B2 (ja) * 2003-12-01 2012-03-07 日本電気株式会社 電流駆動型デバイスの駆動回路、電流駆動型装置及びその駆動方法
US7545928B1 (en) * 2003-12-08 2009-06-09 Advanced Micro Devices, Inc. Triple DES critical timing path improvement
US7580519B1 (en) 2003-12-08 2009-08-25 Advanced Micro Devices, Inc. Triple DES gigabit/s performance using single DES engine
DE102004014435A1 (de) * 2004-03-24 2005-11-17 Siemens Ag Anordnung mit einem integrierten Schaltkreis
US7885405B1 (en) 2004-06-04 2011-02-08 GlobalFoundries, Inc. Multi-gigabit per second concurrent encryption in block cipher modes
US7526085B1 (en) 2004-07-13 2009-04-28 Advanced Micro Devices, Inc. Throughput and latency of inbound and outbound IPsec processing
US7783037B1 (en) 2004-09-20 2010-08-24 Globalfoundries Inc. Multi-gigabit per second computing of the rijndael inverse cipher
US7921301B2 (en) * 2005-05-17 2011-04-05 Dot Hill Systems Corporation Method and apparatus for obscuring data on removable storage devices
JP2007011517A (ja) * 2005-06-29 2007-01-18 Yamaha Corp 集積回路装置
JP4890976B2 (ja) * 2005-08-31 2012-03-07 キヤノン株式会社 暗号処理装置
US7646867B2 (en) * 2005-09-09 2010-01-12 Netapp, Inc. System and/or method for encrypting data
JP2007128603A (ja) * 2005-11-04 2007-05-24 Matsushita Electric Ind Co Ltd メモリ回路
KR100826648B1 (ko) * 2006-01-09 2008-05-06 주식회사 하이닉스반도체 오토리프레쉬 신호 펄스폭 조절회로 및 오토리프레쉬를위한 내부로우어드레스 생성회로
US8681996B2 (en) * 2007-07-31 2014-03-25 Lsi Corporation Asymmetric key wrapping using a symmetric cipher
US8341330B2 (en) * 2008-01-07 2012-12-25 Macronix International Co., Ltd. Method and system for enhanced read performance in serial peripheral interface
US8918589B2 (en) 2008-04-22 2014-12-23 Panasonic Corporation Memory controller, memory system, semiconductor integrated circuit, and memory control method
US8134885B2 (en) * 2009-11-24 2012-03-13 Bae Systems Information And Electronic Systems Integration Inc. High-speed compression architecture for memory
JP4947395B2 (ja) 2010-01-07 2012-06-06 横河電機株式会社 半導体試験装置
US9298918B2 (en) 2011-11-30 2016-03-29 Elwha Llc Taint injection and tracking
US9465657B2 (en) 2011-07-19 2016-10-11 Elwha Llc Entitlement vector for library usage in managing resource allocation and scheduling based on usage and priority
US9575903B2 (en) 2011-08-04 2017-02-21 Elwha Llc Security perimeter
US8813085B2 (en) 2011-07-19 2014-08-19 Elwha Llc Scheduling threads based on priority utilizing entitlement vectors, weight and usage level
US8943313B2 (en) 2011-07-19 2015-01-27 Elwha Llc Fine-grained security in federated data sets
US9443085B2 (en) 2011-07-19 2016-09-13 Elwha Llc Intrusion detection using taint accumulation
US9471373B2 (en) 2011-09-24 2016-10-18 Elwha Llc Entitlement vector for library usage in managing resource allocation and scheduling based on usage and priority
US9798873B2 (en) 2011-08-04 2017-10-24 Elwha Llc Processor operable to ensure code integrity
US9558034B2 (en) 2011-07-19 2017-01-31 Elwha Llc Entitlement vector for managing resource allocation
US8955111B2 (en) 2011-09-24 2015-02-10 Elwha Llc Instruction set adapted for security risk monitoring
US9098608B2 (en) 2011-10-28 2015-08-04 Elwha Llc Processor configured to allocate resources using an entitlement vector
US9460290B2 (en) 2011-07-19 2016-10-04 Elwha Llc Conditional security response using taint vector monitoring
US9170843B2 (en) 2011-09-24 2015-10-27 Elwha Llc Data handling apparatus adapted for scheduling operations according to resource allocation based on entitlement
JP5382163B2 (ja) * 2012-04-26 2014-01-08 富士通セミコンダクター株式会社 半導体メモリ、半導体メモリの動作方法およびシステム
US9910473B2 (en) * 2013-03-14 2018-03-06 Silicon Storage Technology, Inc. Power management for a memory device
US9384791B1 (en) * 2014-12-30 2016-07-05 Altera Corporation Apparatus and method for sense amplifier offset cancellation
WO2018106570A1 (en) * 2016-12-09 2018-06-14 Cryptography Research, Inc. Programmable block cipher with masked inputs
US10884656B2 (en) * 2017-06-16 2021-01-05 Microsoft Technology Licensing, Llc Performing background functions using logic integrated with a memory
KR102698036B1 (ko) * 2019-04-10 2024-08-22 에스케이하이닉스 주식회사 반도체장치
CN111752223B (zh) * 2020-06-29 2022-04-01 配天机器人技术有限公司 信号配置方法、输入输出设备及计算机存储介质

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4835733A (en) 1985-09-30 1989-05-30 Sgs-Thomson Microelectronics, Inc. Programmable access memory
JPH0370055A (ja) * 1989-08-09 1991-03-26 Seiko Instr Inc 半導体集積回路装置
JPH0482082A (ja) * 1990-07-25 1992-03-16 Hitachi Ltd 半導体記憶装置
JPH04159691A (ja) * 1990-10-24 1992-06-02 Nec Corp 同期式半導体記憶装置
JPH06215160A (ja) * 1992-08-25 1994-08-05 Texas Instr Inc <Ti> データ処理方法および装置
US5528549A (en) * 1993-05-28 1996-06-18 Texas Instruments Incorporated Apparatus, systems and methods for distributed signal processing
JPH07122065A (ja) * 1993-10-20 1995-05-12 Kokusai Electric Co Ltd メモリ制御回路
US5721860A (en) * 1994-05-24 1998-02-24 Intel Corporation Memory controller for independently supporting synchronous and asynchronous DRAM memories
JPH0845269A (ja) 1994-07-27 1996-02-16 Hitachi Ltd 半導体記憶装置
US5848247A (en) * 1994-09-13 1998-12-08 Hitachi, Ltd. Microprocessor having PC card interface
US5701438A (en) * 1995-09-29 1997-12-23 Intel Corporation Logical relocation of memory based on memory device type
JP3627116B2 (ja) * 1996-01-22 2005-03-09 株式会社ルネサステクノロジ 半導体集積回路及び半導体集積回路装置
JP3075184B2 (ja) * 1996-08-02 2000-08-07 日本電気株式会社 演算処理機能付主記憶システム及びその制御方法
KR100200763B1 (ko) * 1996-11-30 1999-06-15 윤종용 반도체 메모리 장치의 컬럼 선택 라인 인에이블 회로
JPH10269768A (ja) 1997-03-26 1998-10-09 Mitsubishi Electric Corp 半導体集積回路
US6088761A (en) * 1997-03-31 2000-07-11 Sun Microsystems, Inc. Reduced pin system interface
JPH10283777A (ja) * 1997-04-04 1998-10-23 Mitsubishi Electric Corp Ｓｄｒａｍコアと論理回路を単一チップ上に混載した半導体集積回路装置およびｓｄｒａｍコアのテスト方法
US6185704B1 (en) * 1997-04-11 2001-02-06 Texas Instruments Incorporated System signaling schemes for processor and memory module
JP3189727B2 (ja) * 1997-04-15 2001-07-16 日本電気株式会社 コプロセッサ内蔵パケット型メモリｌｓｉ、それを用いたメモリシステム及びそれらの制御方法
US5953738A (en) 1997-07-02 1999-09-14 Silicon Aquarius, Inc DRAM with integral SRAM and arithmetic-logic units
JPH11213665A (ja) 1998-01-26 1999-08-06 Mitsubishi Electric Corp 半導体回路装置およびその使用方法
JP3490887B2 (ja) 1998-03-05 2004-01-26 シャープ株式会社 同期型半導体記憶装置
JP3741534B2 (ja) * 1998-03-24 2006-02-01 株式会社リコー 半導体メモリ
JPH11328008A (ja) * 1998-05-19 1999-11-30 Nec Corp データ処理機能付メモリｌｓｉ
JP2000030435A (ja) * 1998-07-10 2000-01-28 Nec Corp 半導体集積回路
US5953243A (en) * 1998-09-30 1999-09-14 International Business Machines Corporation Memory module identification
KR100390241B1 (ko) * 1998-12-31 2003-08-19 주식회사 하이닉스반도체 라이트 동작시 셀 데이터 보장장치
JP2000285694A (ja) * 1999-03-30 2000-10-13 Mitsubishi Electric Corp 半導体記憶装置および半導体記憶装置を搭載する半導体集積回路装置
JP2001035148A (ja) * 1999-07-23 2001-02-09 Sanyo Electric Co Ltd データ処理装置
KR20010018808A (ko) * 1999-08-23 2001-03-15 윤종용 다수개의 메모리 블락들 중 소정의 메모리 블락을 선택함에 있어 데이터 라인상의 데이터 충돌을 방지하고 메모리 블락, 로직 블락 및 비스트 회로를 분리하여 테스트 가능토록 하는 메모리 로직 복합 반도체장치
JP2001093275A (ja) * 1999-09-20 2001-04-06 Mitsubishi Electric Corp 半導体集積回路装置
US6473831B1 (en) * 1999-10-01 2002-10-29 Avido Systems Corporation Method and system for providing universal memory bus and module
US6246626B1 (en) * 2000-07-28 2001-06-12 Micron Technology, Inc. Protection after brown out in a synchronous memory
JP2002108691A (ja) * 2000-09-29 2002-04-12 Mitsubishi Electric Corp 半導体記憶装置および半導体記憶装置の制御方法

Also Published As

Publication number Publication date
JP2002175689A (ja) 2002-06-21
TW521276B (en) 2003-02-21
KR20020025660A (ko) 2002-04-04
US6728827B2 (en) 2004-04-27
EP1199724B1 (en) 2003-09-17
KR100422490B1 (ko) 2004-03-11
DE60100779D1 (de) 2003-10-23
EP1199724A1 (en) 2002-04-24
US20020040420A1 (en) 2002-04-04

Similar Documents

Publication Publication Date Title
DE60100779T2 (de) Halbleiteranordnung mit einer unkomplizierten Schnittstelle sowie einer logischen Schaltung und einer eingebauten Speicheranordnung
DE102020104367A1 (de) Refresh-befehlssteuerung für eine hostunterstützung einer rowhammer-mitigation
DE102010030742B4 (de) Phasenwechselspeicher in einem doppelreihigen Speichermodul
DE69913366T2 (de) Lese/schreibe-puffern für ein komplettes verdecken des auffrischen eines halbleiterspeichers und verfahren zum betreiben derselben
DE19982871B4 (de) Speichersystem mit jeweils einen Speichermodul-Controller enthaltenden Speichermodulen
DE69411428T2 (de) Mit einem externen Taktsignal synchronisierte Halbleiterspeicheranordnung zum Ausgeben von Datenbits durch eine kleine Anzahl von Datenleitungen
DE69232458T2 (de) Programmierbare Zeitsteuerung für Speicher
DE69422349T2 (de) Dynamische Direktzugriffspeicher-Anordnung für schnellen sequentiellen Zugriff, mit Leseverstärkern, die unabhängig vom Zeilen-Adresspuffer sind und als Cache-Speicher dienen
DE19983737B3 (de) System zum Neuordnen von Befehlen, die von einer Speichersteuerung zu Speichervorrichtungen ausgegeben werden, unter Verhinderung von Kollision
DE102019118638A1 (de) Ein-Chip-System, das ein Training des Tastgrades des Schreibtakts unter Verwendung eines Modus-Register-Schreibbefehls durchführt, Betriebsverfahren des Ein-Chip-Systems, elektronische Vorrichtung mit dem Ein-Chip-System
DE112017006599T5 (de) Programmierbare datenstruktur zum wiederholten schreiben in einen speicher
DE112016004243T5 (de) Hybrides Auffrischen mit verborgenen Auffrischungen und externen Auffrischungen
TWI241519B (en) Method and apparatus for supplementary command bus
CN1732446B (zh) 用于对存储器写入的方法
CN107667403A (zh) 长突发长度的内部连续行存取
DE102006028683B4 (de) Parallele Datenpfadarchitektur
DE60103601T2 (de) Leicht steuerbare Halbleiterspeicheranordnung mit einer eingebauten logischen Schaltung sowie entsprechendes Steuerverfahren
DE102023110723A1 (de) Randomisierung von gezielten auffrischungsverwaltungs(directed refresh management - drfm)-pseudo-zielzeilenauffrischungs(pseudo target row refresh - pttr)-befehlen
KR20030057470A (ko) 고속 동작 반도체 메모리 장치 및 그의 사용 및 설계 방법
DE102006030373A1 (de) Halbleiterspeichervorrichtung
DE102006002888B4 (de) Direktzugriffsspeicher mit niedriger Anfangslatenz
DE60035630T2 (de) Hierarchische Vorausladung in Halbleiterspeicheranordnungen
CN115374030A (zh) 具有存储器发起的命令插入的存储器以及相关联系统、装置和方法
DE102007062930A1 (de) Speichervorrichtung mit mehreren Konfigurationen
DE69525764T2 (de) Verfahren und struktur zur verwendung einer dram-matrix für einen zweite-stufe-cachespeicher

Legal Events

Date Code Title Description
8364 No opposition during term of opposition