DE60030896D1 - Testmuster-Kompression für eine Testumgebung von integrierten Schaltungen - Google Patents

Testmuster-Kompression für eine Testumgebung von integrierten Schaltungen

Info

Publication number
DE60030896D1
DE60030896D1 DE60030896T DE60030896T DE60030896D1 DE 60030896 D1 DE60030896 D1 DE 60030896D1 DE 60030896 T DE60030896 T DE 60030896T DE 60030896 T DE60030896 T DE 60030896T DE 60030896 D1 DE60030896 D1 DE 60030896D1
Authority
DE
Germany
Prior art keywords
test
integrated circuit
scan
symbolic expressions
symbolic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60030896T
Other languages
English (en)
Other versions
DE60030896T2 (de
Inventor
Janusz Rajskli
Jerzy Tyszer
Mark Kassab
Nilanjan Mukherjee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mentor Graphics Corp
Original Assignee
Mentor Graphics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mentor Graphics Corp filed Critical Mentor Graphics Corp
Publication of DE60030896D1 publication Critical patent/DE60030896D1/de
Application granted granted Critical
Publication of DE60030896T2 publication Critical patent/DE60030896T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318335—Test pattern compression or decompression
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
DE60030896T 1999-11-23 2000-11-15 Testmuster-Kompression für eine Testumgebung von integrierten Schaltungen Expired - Lifetime DE60030896T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US16744699P 1999-11-23 1999-11-23
US167446P 1999-11-23
US09/619,985 US6327687B1 (en) 1999-11-23 2000-07-20 Test pattern compression for an integrated circuit test environment
US619985 2000-07-20

Publications (2)

Publication Number Publication Date
DE60030896D1 true DE60030896D1 (de) 2006-11-02
DE60030896T2 DE60030896T2 (de) 2007-09-20

Family

ID=26863184

Family Applications (2)

Application Number Title Priority Date Filing Date
DE60030896T Expired - Lifetime DE60030896T2 (de) 1999-11-23 2000-11-15 Testmuster-Kompression für eine Testumgebung von integrierten Schaltungen
DE60018101T Expired - Lifetime DE60018101T2 (de) 1999-11-23 2000-11-15 Testmuster-kompression für eine testumgebung von integrierten schaltungen

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE60018101T Expired - Lifetime DE60018101T2 (de) 1999-11-23 2000-11-15 Testmuster-kompression für eine testumgebung von integrierten schaltungen

Country Status (7)

Country Link
US (5) US6327687B1 (de)
EP (1) EP1236111B1 (de)
JP (1) JP3920640B2 (de)
AT (2) ATE289094T1 (de)
DE (2) DE60030896T2 (de)
HK (1) HK1049215A1 (de)
WO (1) WO2001038981A1 (de)

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US20090259900A1 (en) 2009-10-15
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US20070016836A1 (en) 2007-01-18
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US20020053057A1 (en) 2002-05-02
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