DE3933965C2 - - Google Patents

Info

Publication number
DE3933965C2
DE3933965C2 DE3933965A DE3933965A DE3933965C2 DE 3933965 C2 DE3933965 C2 DE 3933965C2 DE 3933965 A DE3933965 A DE 3933965A DE 3933965 A DE3933965 A DE 3933965A DE 3933965 C2 DE3933965 C2 DE 3933965C2
Authority
DE
Germany
Prior art keywords
layer
gate
gate structure
insulating layer
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3933965A
Other languages
German (de)
English (en)
Other versions
DE3933965A1 (de
Inventor
Teruyuki Itami Hyogo Jp Shimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3933965A1 publication Critical patent/DE3933965A1/de
Application granted granted Critical
Publication of DE3933965C2 publication Critical patent/DE3933965C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/061—Manufacture or treatment of FETs having Schottky gates
    • H10D30/0612—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs
    • H10D30/0616—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs using processes wherein the final gate is made before the completion of the source and drain regions, e.g. gate-first processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
DE3933965A 1988-10-12 1989-10-11 Mesfet und verfahren zu dessen herstellung Granted DE3933965A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63258007A JPH02103939A (ja) 1988-10-12 1988-10-12 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3933965A1 DE3933965A1 (de) 1990-04-19
DE3933965C2 true DE3933965C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-12-03

Family

ID=17314241

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3933965A Granted DE3933965A1 (de) 1988-10-12 1989-10-11 Mesfet und verfahren zu dessen herstellung

Country Status (3)

Country Link
US (1) US4977100A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH02103939A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3933965A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02138750A (ja) * 1988-08-24 1990-05-28 Mitsubishi Electric Corp 半導体装置の製造方法
US5141891A (en) * 1988-11-09 1992-08-25 Mitsubishi Denki Kabushiki Kaisha MIS-type semiconductor device of LDD structure and manufacturing method thereof
US5166771A (en) * 1990-01-12 1992-11-24 Paradigm Technology, Inc. Self-aligning contact and interconnect structure
US5483104A (en) * 1990-01-12 1996-01-09 Paradigm Technology, Inc. Self-aligning contact and interconnect structure
US5264379A (en) * 1990-05-14 1993-11-23 Sumitomo Electric Industries, Inc. Method of making a hetero-junction bipolar transistor
DE4032411A1 (de) * 1990-10-12 1992-04-16 Daimler Benz Ag Verfahren zur herstellung von t-gate-elektroden
US5116774A (en) * 1991-03-22 1992-05-26 Motorola, Inc. Heterojunction method and structure
JPH05326561A (ja) * 1992-05-22 1993-12-10 Nec Corp 電界効果トランジスタの製造方法
US5336930A (en) * 1992-06-26 1994-08-09 The United States Of America As Represented By The Secretary Of The Air Force Backside support for thin wafers
JP3170141B2 (ja) * 1993-07-27 2001-05-28 株式会社東芝 半導体装置
JPH0786310A (ja) * 1993-09-20 1995-03-31 Mitsubishi Electric Corp 高融点金属ゲート電極の形成方法
US5550065A (en) * 1994-11-25 1996-08-27 Motorola Method of fabricating self-aligned FET structure having a high temperature stable T-shaped Schottky gate contact
JP3336487B2 (ja) * 1995-01-30 2002-10-21 本田技研工業株式会社 高周波トランジスタのゲート電極形成方法
US5620909A (en) * 1995-12-04 1997-04-15 Lucent Technologies Inc. Method of depositing thin passivating film on microminiature semiconductor devices
US5958508A (en) * 1997-03-31 1999-09-28 Motorlola, Inc. Process for forming a semiconductor device
US5888588A (en) * 1997-03-31 1999-03-30 Motorola, Inc. Process for forming a semiconductor device
US6084279A (en) * 1997-03-31 2000-07-04 Motorola Inc. Semiconductor device having a metal containing layer overlying a gate dielectric
US6153519A (en) * 1997-03-31 2000-11-28 Motorola, Inc. Method of forming a barrier layer
US6255204B1 (en) 1999-05-21 2001-07-03 Motorola, Inc. Method for forming a semiconductor device
US7081416B2 (en) * 2003-04-04 2006-07-25 Micron Technology, Inc. Methods of forming field effect transistor gates

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4400866A (en) * 1980-02-14 1983-08-30 Xerox Corporation Application of grown oxide bumper insulators to a high-speed VLSI SASMESFET
JPS58101466A (ja) * 1981-12-14 1983-06-16 Hitachi Ltd 半導体装置の製造方法
JPS5950567A (ja) * 1982-09-16 1984-03-23 Hitachi Ltd 電界効果トランジスタの製造方法
JPS6086866A (ja) * 1983-10-19 1985-05-16 Matsushita Electronics Corp 電界効果トランジスタおよびその製造方法
GB2156579B (en) * 1984-03-15 1987-05-07 Standard Telephones Cables Ltd Field effect transistors
US4855246A (en) * 1984-08-27 1989-08-08 International Business Machines Corporation Fabrication of a gaas short channel lightly doped drain mesfet
JPS61154046A (ja) * 1984-12-26 1986-07-12 Nec Corp 半導体装置
JPS6292481A (ja) * 1985-10-18 1987-04-27 Nec Corp 半導体装置の製造方法
EP0268298B1 (en) * 1986-11-20 1995-04-05 Sumitomo Electric Industries Limited Method of producing a Schottky-barrier field effect transistor
US4849376A (en) * 1987-01-12 1989-07-18 Itt A Division Of Itt Corporation Gallium Arsenide Technology Center Self-aligned refractory gate process with self-limiting undercut of an implant mask
US4839311A (en) * 1987-08-14 1989-06-13 National Semiconductor Corporation Etch back detection
JPS6489470A (en) * 1987-09-30 1989-04-03 Mitsubishi Electric Corp Manufacture of semiconductor device
US4829025A (en) * 1987-10-02 1989-05-09 Advanced Micro Devices, Inc. Process for patterning films in manufacture of integrated circuit structures
JPH0787195B2 (ja) * 1987-10-22 1995-09-20 三菱電機株式会社 ショットキゲート電界効果トランジスタの製造方法
US4863879A (en) * 1987-12-16 1989-09-05 Ford Microelectronics, Inc. Method of manufacturing self-aligned GaAs MESFET

Also Published As

Publication number Publication date
US4977100A (en) 1990-12-11
DE3933965A1 (de) 1990-04-19
JPH02103939A (ja) 1990-04-17

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee