DE3923619A1 - Halbleitereinrichtung und verfahren zu deren herstellung - Google Patents

Halbleitereinrichtung und verfahren zu deren herstellung

Info

Publication number
DE3923619A1
DE3923619A1 DE3923619A DE3923619A DE3923619A1 DE 3923619 A1 DE3923619 A1 DE 3923619A1 DE 3923619 A DE3923619 A DE 3923619A DE 3923619 A DE3923619 A DE 3923619A DE 3923619 A1 DE3923619 A1 DE 3923619A1
Authority
DE
Germany
Prior art keywords
layer
high resistance
semiconductor
semiconductor device
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE3923619A
Other languages
German (de)
English (en)
Other versions
DE3923619C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Junichi Mitsuhashi
Shinichi Satoh
Hideki Genjyo
Yoshio Kohno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3923619A1 publication Critical patent/DE3923619A1/de
Application granted granted Critical
Publication of DE3923619C2 publication Critical patent/DE3923619C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors

Landscapes

  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE3923619A 1988-07-19 1989-07-17 Halbleitereinrichtung und verfahren zu deren herstellung Granted DE3923619A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63179887A JPH0727980B2 (ja) 1988-07-19 1988-07-19 高抵抗層を有する半導体装置

Publications (2)

Publication Number Publication Date
DE3923619A1 true DE3923619A1 (de) 1990-01-25
DE3923619C2 DE3923619C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-04-08

Family

ID=16073634

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3923619A Granted DE3923619A1 (de) 1988-07-19 1989-07-17 Halbleitereinrichtung und verfahren zu deren herstellung

Country Status (4)

Country Link
US (1) US5093706A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH0727980B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR930006275B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3923619A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461000A (en) * 1994-07-05 1995-10-24 Taiwan Semiconductor Manufacturing Company Ltd. Method of manufacturing dielectric as load resistor in 4T SRAM
US5578854A (en) * 1995-08-11 1996-11-26 International Business Machines Corporation Vertical load resistor SRAM cell
US5665629A (en) * 1995-08-11 1997-09-09 International Business Machines Corporation Four transistor SRAM process
US5683930A (en) * 1995-12-06 1997-11-04 Micron Technology Inc. SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and methods of making
KR100204012B1 (ko) * 1996-05-13 1999-06-15 김영환 고저항 부하형 스태틱램 셀 및 그 제조방법
US5986922A (en) * 1997-09-30 1999-11-16 Alliance Semiconductor Method of and apparatus for increasing load resistance within an SRAM array
US6303965B1 (en) * 1999-08-20 2001-10-16 Micron Technology, Inc. Resistor constructions and methods of forming resistor constructions
EP3327756B1 (en) * 2016-11-24 2019-11-06 Melexis Technologies NV Die edge integrity monitoring system and corresponding method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4406051A (en) * 1979-09-11 1983-09-27 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device
DE3702409A1 (de) * 1986-02-03 1987-08-06 Intel Corp Verfahren zur herstellung eines elektrischen widerstandes in einem halbleiterbaustein

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4131902A (en) * 1977-09-30 1978-12-26 Westinghouse Electric Corp. Novel bipolar transistor with a dual-dielectric tunnel emitter
JPS6188548A (ja) * 1984-10-08 1986-05-06 Toshiba Corp 半導体装置
JPS61134055A (ja) * 1984-12-04 1986-06-21 Sony Corp 半導体装置の製造方法
JPS6230351A (ja) * 1985-04-25 1987-02-09 Nec Corp 半導体装置の製造方法
US4641173A (en) * 1985-11-20 1987-02-03 Texas Instruments Incorporated Integrated circuit load device
US4755480A (en) * 1986-02-03 1988-07-05 Intel Corporation Method of making a silicon nitride resistor using plasma enhanced chemical vapor deposition
US4786612A (en) * 1986-02-03 1988-11-22 Intel Corporation Plasma enhanced chemical vapor deposited vertical silicon nitride resistor
JPS62195179A (ja) * 1986-02-21 1987-08-27 Mitsubishi Electric Corp 電界効果トランジスタ
US4823181A (en) * 1986-05-09 1989-04-18 Actel Corporation Programmable low impedance anti-fuse element
US4888820A (en) * 1988-12-06 1989-12-19 Texas Instruments Incorporated Stacked insulating film including yttrium oxide
US4931897A (en) * 1989-08-07 1990-06-05 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor capacitive element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4406051A (en) * 1979-09-11 1983-09-27 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device
DE3702409A1 (de) * 1986-02-03 1987-08-06 Intel Corp Verfahren zur herstellung eines elektrischen widerstandes in einem halbleiterbaustein

Also Published As

Publication number Publication date
KR930006275B1 (ko) 1993-07-09
US5093706A (en) 1992-03-03
DE3923619C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-04-08
KR900002321A (ko) 1990-02-28
JPH0228970A (ja) 1990-01-31
JPH0727980B2 (ja) 1995-03-29

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee